Dalsa Piranha 2 P2-2-30 Series, User Manual

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21 Piranha 2 User’s Manual
03-032-00493-14 Teledyne DALSA
Symbol Definition Min (ns) Typ
(ns) Max
(ns)
p hotosite reset
tPR_SET The nom inal tim e that the p hoto sites are
integrating. Clock synchronization w ill
lead to integration tim e jitter, w hich is
show n in the sp ecification as +/ - valu es.
The u ser shou ld com m and tim es greater
than these to ensu re p rop er charge
transfer from the p hotosites. Failu re to
m eet this requ irem ent m ay resu lt in
bloom ing in the H orizontal Shift Register. 2,000+/ -200
*SMART EXSYN C refers to exp osu re m od e 4. Refer to section 3.9 Setting Line Rate an d
Exp osu re Mod e for fu rther inform ation on exp osu re m od es.
Table 7: Piranha 2 30MHz Timing (Fixed Integration Mode)
N ote: All valu es are p relim in ary for the Piranh a 2 30MH z
Symbol Definition Min (ns) Typ
(ns) Max
(ns)
tw SYN C The m inim u m low w id th of the EXSYN C
p u lse w hen not in SMART EXSYN C
m od e. 132
tw SYN C
(SMART)
*
The m inim u m low w id th of the EXSYN C
p u lse w hen in SMART EXSYN C m od es to
gu arantee the p hotosites are reset.
2,640
tw SYN C_IN T The m inim u m w id th of the high p u lse
w hen the ―SMART EXSYNC‖ feature is
tu rned off 132
tw SYN C_IN T
(SMART)
*
Is the integration time w hen the ―SMART
EXSYNC‖ feature is available and turned
on. N ote that the m inim u m tim e is
necessary to gu arantee p rop er op eration.
2,000
tLIN E PERIOD
(t
LP
)
The m inim u m and m axim u m line tim es
m ad e u p of tTransfer, tREADOUT p lu s
tOVERH EAD to m eet sp ecifications. 140487 (8K2T)
70,170 (4K2T)
36,378 (2K2T)
19,483 (1K2T)
10
6
tTransfer The tim e from the recep tion of the falling
ed ge of EXSYN C to the rising ed ge of
LVAL w hen pretrigger is set to zero.
Pretrigger red u ces the nu m ber of clocks to
the rising edge of LVAL but doesn’t
change the tim e to the first valid p ixel. If
the fixed integration tim e m od e of
op eration is available and selected then
the integration tim e is ad d ed to the
sp ecified valu e. 1,874 +/ -66
tw Fixed Int. Fixed Integration Tim e m od e of op eration
for variable exsync frequ ency. 800 t
LP
–
2,000
tREADOUT Is the nu m ber of p ixels p er tap tim es the
read ou t clock p eriod . Pretrigger = 0. 138033 (8K2T)
33, 792 (4K4T)
67,584 (4K2T)
33,792 (2K2T)
16,896 (1K2T)
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