DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Pin Description (continued)
PIN
SO,
PDIP
EDIP
PLCC
TQFP
NAME
FUNCTION
22
2, 3,
16, 20,
21, 22
1, 11,
13, 18,
26
4, 6, 10,
15, 20,
23, 25,
27, 32
N.C.
No Connection. This pin should remain unconnected. Pin 21 is
RCLR
for the
DS12887A/DS12C887A. On the EDIP, these pins are missing by design.
17
17
21
18
DS
D ata S tr ob e or Read Inp ut. The D S p i n has tw o m od es of op er ati on d ep end i ng on
the l evel of the M O T p i n. W hen the M O T p i n i s connected to V
C C
, M otor ol a b us
ti m i ng i s sel ected . In thi s m od e, D S i s a p osi ti ve p ul se d ur i ng the l atter p or ti on of the
b us cycl e and i s cal l ed d ata str ob e. D ur i ng r ead cycl es, D S si g ni fi es the ti m e that the
device i s to d r i ve the b i d i r ecti onal b us. In w r i te cycl es, the tr ai l i ng ed g e of D S causes
the device to l atch the w r i tten d ata. W hen the M O T p i n i s connected to GN D , Intel
b us ti m i ng i s sel ected . D S i d enti fi es the ti m e p er i od w hen the device d r i ves the b us
w i th r ead d ata. In thi s m od e, the D S p i n op er ates i n a si m i l ar fashi on as the outp ut-
enab l e (
O E
) si g nal on a g ener i c RAM .
18
18
22
19
RESET
Active-Low Reset Input. The
RESET
pin has no effect on the clock, calendar, or
RAM. On power-up, the
RESET
pin can be held low for a time to allow the power
supply to stabilize. The amount of time that
RESET
is held low is dependent on the
application. However, if
RESET
is used on power-up, the time
RESET
is low should
exceed 200ms to ensure that the internal timer that controls the device on power-
up has timed out. When
RESET
is low and V
CC
is above V
PF
, the following occurs:
A. Periodic interrupt-enable (PIE) bit is cleared to 0.
B. Alarm interrupt-enable (AIE) bit is cleared to 0.
C. Update-ended interrupt-enable (UIE) bit is cleared to 0.
D. Periodic-interrupt flag (PF) bit is cleared to 0.
E. Alarm-interrupt flag (AF) bit is cleared to 0.
F. Update-ended interrupt flag (UF) bit is cleared to 0.
G. Interrupt-request status flag (IRQF) bit is cleared to 0.
H.
IRQ
pin is in the high-impedance state.
I. The device is not accessible until
RESET
is returned high.
J. Square-wave output-enable (SQWE) bit is cleared to 0.
In a typical application,
RESET
can be connected to V
CC
. This connection allows
the device to go in and out of power fail without affecting any of the control
registers.
Real-Time Clock
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