Daewoo DV-F24S, Service Manual

Page: 18 / 110

16
This signal from Pin 4 of IC301 is then passed through a sub-deemphasis and Buffer and fed to Pin 5 of IC301.
The signal input to Pin 5 of IC301 is fed to the YNR through a LPF. The YNR circuit gives considerable noise reduction
effects. The signal from the YNR circuit is fed to the Y/C Mixer circuit through the Non-linear Deemphasis, the Double High
Pass Noise Canceller (DHPC), and the Picture Controller circuit. The signal is then mixed with the playback colour signal
and the PB Video Signal is obtained from Pin 16 of IC301 through Quasi-Vertical/Quasi-Horizontal (QV/QH) Insertion circuit
and the Video Output Amplifier (about 6dB amplification). The output of Pin 16 (approximately 2Vp-p) is input to the Buffer
circuit (consists of Q309 and R323).
D. Signal flow of the PAL colour in the playback mode
FM
AGC
Double
Limiter
FM
Demod
L P F
Main
De-empha
L P F
Sub-deempha
& buffer
Y N R
N L
De-empha
Double HP
Noise Can
Picture
Controller
IH Delay
CCD
IC302
Video
AMP
QV/QH
Y/C
MIX
R322
R323
Q309
TO OSD CIRCUIT
6
$
%
%
0
*
8
!
Y-FM input
BLOCK 3. PLAYBACK LUMINANCE SIGNAL FLOW
Buffer
1.3MHz
LPF
PB colour input
u
ACC
AMP
Main
Conv
4.43MHz
BPF
627KHz 627KHz 5.06MHz
± 627KHz
NAP
PB AMP
/Killer
2H Delay
IC302
Y/C
Mixer
+ =
$
@
“ q
E
w
From. PB luminance
signal
5.06MHz
fsc (4.433619MHz)
PB SECAM
Colour input
BLOCK 4. PB PAL COLOUR SIGNAL FLOW
4.43MHz
4.43MHz
IC303
!
)
PAL : LOW
MESECAM : HIGH