18
CIRCUIT OPERATION MANUAL
Data
Parity
No Error
Uncorrectible Packet
No Error
BYTE CLK
P A C K E T
STR OUT
E R R O R
BY T E D A T A
Parallel Data Output Timing
TS Output is made by the Serial or Parallel function.
The relationship between TS output Data and Control signal is showing in the following diagram. If an error occurs Data is
ignored, and the Data in the Valid area is valid.
Parallel Output Timing
PIN NO MARK
DESCRIPTION
CURRENT RIPPLE(MAX)
1
LNB A
POWER INPUT OF LNB A
2
NC
3
5V(RF)
5V OF RF-AMP
20mA(TYP.) 20mVp-p
4
AGC
AGC MONITORING
5
5V
5V OF 2’nd AMP & ZERO-IF IC
20mA(TYP.) 20mVp-p
6
GND
7
VT
TUNING VOLTAGE 30V
* 20mVp-p
8
I
I SIGNAL MONITORING
9
Q
Q SIGNAL MONITORING
10
5V
POWER OF AGC AMP
10mA(TYP.) 20mVp-p
11
3.3V
POWER OF FEC IC
200mA(MAX.) 20mVp-p
12
F22
22kHz OUTPUT(serial 100ohm)
13
1.8V
PLL POWER of FEC IC
120mA(MAX.) 20mVp-p
14
RESET
ACTIVE LOW(serial 2Kohm)
15
ERROR OUT
ERROR OUTPUR(serial 100ohm)
16
FSTART
FSTART(serial 100ohm)
17
VALID
DATA VALID(serial 100ohm)
18
BCLK
BYTE CLOCK(serial 47ohm)
19-26
D0-D7
DATA OUTPUT(serial 100ohm)
27
DATA
I2C DATA(serial 100ohm)
28
CLOCK
I2C CLOCK(serial 100ohm)
Summary of Contents for DSD-9255E
Page 17: ...16 CIRCUIT OPERATION MANUAL EMI Interface Timing...
Page 40: ...39 SCHEMATIC DIAGRAM...
Page 41: ...40 SCHEMATIC DIAGRAM...
Page 42: ...41 SCHEMATIC DIAGRAM...
Page 43: ...42 SCHEMATIC DIAGRAM...
Page 44: ...43 SCHEMATIC DIAGRAM...
Page 45: ...44 SCHEMATIC DIAGRAM...
Page 46: ...45 PARTS PLACEMENT ARRANGEMENT...
Page 47: ...46 PARTS PLACEMENT ARRANGEMENT...
Page 48: ...47 PARTS PLACEMENT ARRANGEMENT DSD 9255 FRONT DSD 9256 FRONT...
Page 49: ...48 PARTS PLACEMENT ARRANGEMENT...
Page 50: ...686 AHYEON DONG MAPO GU SEOUL KOREA C P O BOX 8003 SEOUL KOREA DAEWOO ELECTRONICS Corp...