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ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B

M8C Instruction Set

4.17

Jump if Not Zero

JNZ

If the Zero Flag is not set, jump to the address indicated by the sum of the argument and the current

PC+1

. The current PC value is defined as the PC value that corresponds to the ROM address of the

first byte of the

JNZ

instruction.

The

JNZ

instruction uses a two-byte instruction format where the lower nibble of the first byte is used

for the upper 4 bits of the 12-bit relative address. This causes an effective 4-bit opcode. Therefore,
the following are all valid opcode bytes for the

JNZ

instruction: 0xB0, 0xB1, 0xB2,..., 0xBF.

Instructions

Operation

Opcode

Cycles Bytes

Mnemonic

Argument

JNZ

expr

0xBx

Conditional
Flags:

CF
ZF

Unaffected.
Unaffected.

Example:

0000

_main:

0000

55 3C 02

[08]

mov [3Ch], 2

0003

16 3C 01

[09]

sub [3Ch], 1

;2-1=1 CF=0, ZF=0

0006

B0 02

[05]

jnz SubFun

;jump to SubFun

0008

[04]

halt

0009
0009

SubFun:

0009

[04]

nop

PC 1







, 2048

–

k 2047

 





[+] Feedback

Summary of Contents for PSoC DESIGNER ImageCraft M8C

Page 1: ...ImageCraft Assembly Language Guide Document 001 44475 Rev B Cypress Semiconductor 198 Champion Court San Jose CA 95134 1709 Phone USA 800 858 1810 Phone Intnl 408 943 2600 http www cypress com Feedback ...

Page 2: ...tent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom soft ware and or firmware in support of licensee product to be use...

Page 3: ... Source Immediate 18 2 5 2 Source Direct 19 2 5 3 Source Indexed 19 2 5 4 Destination Direct 20 2 5 5 Destination Indexed 20 2 5 6 Destination Direct Source Immediate 21 2 5 7 Destination Indexed Source Immediate 21 2 5 8 Destination Direct Source Direct 22 2 5 9 Source Indirect Post Increment 22 2 5 10 Destination Indirect Post Increment 23 3 ImageCraft Assembler 25 3 1 Source File Format 25 3 1 ...

Page 4: ...mory MVI 59 No Operation NOP 60 Bitwise OR OR 61 Pop Stack into Register POP 62 Push Register onto Stack PUSH 63 Return RET 64 Return from Interrupt RETI 65 Rotate Left through Carry RLC 66 Absolute Table Read ROMX 67 Rotate Right through Carry RRC 68 Subtract with Borrow SBB 69 Subtract without Borrow SUB 70 Swap SWAP 71 System Supervisor Call SSC 72 Test for Mask TST 73 Bitwise XOR XOR 74 5 Asse...

Page 5: ...Section for Dead Code Elimination SECTION ENDSECTION 94 Suspend Resume Code Compressor OR F 0 ADD SP 0 94 6 Builds and Error Messages 97 6 1 Assemble and Build 97 6 2 Linker Operations 97 6 3 Code Compressor and Dead Code Elimination Error Messages 98 A Reference Tables Appendix 99 A 1 Assembly Syntax Expressions 99 A 2 Operand Constant Formats 99 A 3 Assembler Directives Summary 100 A 4 ASCII Cod...

Page 6: ...6 ImageCraft Assembly Language Guide Document 001 44475 Rev B Contents Feedback ...

Page 7: ...rade information and lists documentation conventions M8C Microprocessor on page 11 Discusses the microprocessor and explains address spaces instruction format and destination of instruction results It also lists all addressing modes and pro vides examples of each ImageCraft Assembler on page 25 Provides assembly language source syntax including labels mnemonics oper ands comments and directives De...

Page 8: ...cements for PSoC software free of charge You can order upgrades from your distributor on CD ROM or download them directly from www cypress com under Software and Drivers Critical updates to system documentation are also available on the Cypress web site 1 3 Documentation Conventions The following are easily identifiable conventions used throughout this guide The following are acronyms used through...

Page 9: ...ll WDR watchdog timer reset X CPU_X register index XRES external reset ZF zero flag Table 1 4 Revision History Revision PDF Creation Date Origin of Change Description of Change May 20 2008 FSU Put the original ImageCraft Assembly Guide in a new template and assigned a Spec Num ber A Sept 11 2008 OGNE PYRS Made changes in the Assembly instructions chapter page 72 B June 06 2011 RAVG Made changes in...

Page 10: ...10 ImageCraft Assembly Language Guide Document 001 44475 Rev B Introduction Feedback ...

Page 11: ...16 bits wide Upon reset A X PC and SP are reset to 0x00 The Flag register CPU_F F is reset to 0x02 indicating that the Z flag is set With each stack operation the SP is automatically incremented or decremented so that it always points at the next stack byte in Random Access Memory RAM If the last byte in the stack is at address 0xFF in RAM the Stack Pointer CPU_SP or SP will wrap to RAM address 0x...

Page 12: ...ore Flash is organized into 64 byte blocks The user need not be concerned with program store page boundaries because the M8C automatically increments the 16 bit CPU_PC register PC on every instruction making the block boundaries invisible to user code Instructions occurring on a 256 byte Flash page boundary with the exception of jump instructions incur an extra M8C clock cycle because the upper by...

Page 13: ... Bank 1 256 Bytes Page 0 256 Bytes SROM Flash M x 64 Byte Blocks LEGEND M Total number of Flash bocks in device n Total number of RAM pages minus 1 in device XIO Register bank selection IOR Register read IOW Register write MR Memory read MW Memory write MW MR IOW IOR XIO DB 7 0 DA 7 0 ID 7 0 PC 15 0 M8C A F SP PC X PAGE Page 1 256 Bytes Page n 256 Bytes Feedback ...

Page 14: ...Z 3F 10 2 MVI expr A 6C 8 2 RLC X expr C Z 13 7 2 SUB A X expr C Z 40 4 1 NOP 6D 4 1 RRC A C Z 14 7 2 SUB expr A C Z 41 9 3 AND reg expr expr Z 6E 7 2 RRC expr C Z 15 8 2 SUB X expr A C Z 42 10 3 AND reg X expr expr Z 6F 8 2 RRC X expr C Z 16 9 3 SUB expr expr C Z 43 9 3 OR reg expr expr Z 70 4 2 AND F expr C Z 17 10 3 SUB X expr expr C Z 44 10 3 OR reg X expr expr Z 71 4 2 OR F expr C Z 18 5 1 PO...

Page 15: ... 4 2 SUB A expr C Z 70 4 2 AND F expr C Z 5A 5 2 MOV expr X 12 6 2 SUB A expr C Z 41 9 3 AND reg expr expr Z 5B 4 1 MOV A X Z 13 7 2 SUB A X expr C Z 42 10 3 AND reg X expr expr Z 5C 4 1 MOV X A 14 7 2 SUB expr A C Z 64 4 1 ASL A C Z 5D 6 2 MOV A reg expr Z 15 8 2 SUB X expr A C Z 65 7 2 ASL expr C Z 5E 7 2 MOV A reg X expr Z 16 9 3 SUB expr expr C Z 66 8 2 ASL X expr C Z 5F 10 3 MOV expr expr 17 ...

Page 16: ...tly affect the register space or the RAM address space The SSC instruction will cause SROM code to run which will modify RAM and the M8C internal registers The second category has only the two PUSH instructions in it The PUSH instructions are unique because they are the only one byte instructions that cause a RAM address to be modified These instructions automatically increment the CPU_SP register...

Page 17: ...essing modes see Addressing Modes on page 18 2 4 3 Three Byte Instructions The three byte instruction formats are the second most prevalent instruction formats These instruc tions need three bytes because they either move data between two addresses in the user accessible address space registers and RAM or they hold 16 bit absolute addresses as the destination of a long jump or long call The first ...

Page 18: ...ese instructions the source value is stored in operand 1 of the instruction The result of these instructions is placed in either the M8C CPU_A CPU_F or CPU_X register as indicated by the instruction s opcode All instructions using the Source Immediate addressing mode are two bytes in length Source Immediate Examples Table 2 7 Source Immediate Opcode Operand 1 Instruction Immediate Value Source Cod...

Page 19: ... off set to determine the address of the source value in RAM or register address space The result of these instructions is placed in either the M8C CPU_A or CPU_X register as indicated by the instruc tion s opcode All instructions using the Source Indexed addressing mode are two bytes in length Source Indexed Examples Table 2 8 Source Direct Opcode Operand 1 Instruction Source Address Source Code ...

Page 20: ...egister or an immediate value as indicated by the instruction s opcode All instructions using the Destination Indexed addressing mode are two bytes in length Destination Indexed Example Table 2 10 Destination Direct Opcode Operand 1 Instruction Destination Address Source Code Machine Code Comments ADD 7 A 04 07 The value in the Accumulator is added to memory at address 7 The result is placed in me...

Page 21: ...on Indexed Source Immediate addressing mode are three bytes in length Destination Indexed Source Immediate Examples Table 2 12 Destination Direct Source Immediate Opcode Operand 1 Operand 2 Instruction Destination Address Immediate Value Source Code Machine Code Comments ADD 7 5 06 07 05 The value in memory at address 7 is added to the immediate value 5 The result is placed in memory at address 7 ...

Page 22: ...RAM page to use with the source address Therefore values from pages other than the current page can be retrieved without changing the Cur rent Page Pointer CUR_PP The pointer is always read from the current RAM page For informa tion on the MVR_PP and CUR_PP registers see the Register Reference chapter in the PSoC Technical Reference Manual The instruction using the Source Indirect Post Increment a...

Page 23: ...dress Therefore values can be stored in pages other than the current page without changing the Current Page Pointer CUR_PP The pointer is always read from the current RAM page For information on the MVR_PP and CUR_PP registers see the Register Reference chapter in the PSoC Technical Reference Manual The instruction using the Destination Indirect Post Increment addressing mode is two bytes in lengt...

Page 24: ...24 ImageCraft Assembly Language Guide Document 001 44475 Rev B M8C Microprocessor Feedback ...

Page 25: ... used in assembly language to machine code that the microcontroller can operate on directly 3 1 Source File Format Assembly language source files for the ImageCraft Assembler have five basic components as listed in Table 3 1 Each line of the source file may hold a single label mnemonic comment or directive Multiple operands or expressions may be used on a single source file line The maximum length...

Page 26: ... a colon A label is assigned the address of the current Program Counter by the Assembler unless the label is defined on a line with an EQU directive See Equate Label EQU on page 87 for more infor mation Labels can be placed on any line including lines with source code as long as the label appears first The Assembler supports three types of labels local global and re usable local Local Labels These...

Page 27: ...e following example has a single global label called SubFun and a re usable local label called MoreFun Notice that while labels do not include the colon when referenced re usable local labels require that a period precede the label string for all instances Re usable local labels are case sensitive 3 1 2 Mnemonics An instruction mnemonic is a two to five letter string that represents one of the mic...

Page 28: ...are most often used as the operands for jump and call instructions to specify the destination address However labels may be used as an argument for any instruction Dot Operator This is used to indicate that the ROM address of the first byte of the instruction should be used as an argument to the instruction Table 3 2 Constants Formats Radix Name Formats Example 127 ASCII Character J mov A J charac...

Page 29: ...sembler i e a sym bol defined in the file 3 1 4 Comments A comment starts with a semicolon or a double slash and goes to the end of a line It is usu ally used to explain the assembly code and may be placed anywhere in the source file The Assem bler ignores comments however they are written to the listing file for reference Table 3 3 Register Formats Type Formats Example User Accessible Registers r...

Page 30: ...tants used in the source file to decimal values and that the machine code is always show in hexadecimal In this case the source code expressed the constant as an octal value 0112 the Assembler represented the same value in decimal 74 and the machine code uses hexadecimal 4A 3 3 Map File Format A project name mp file is created each time the ImageCraft Assembler completes without errors or warnings...

Page 31: ...n Flash For the example below only addresses 0x0000 through 0x002E of the Flash have assigned values according to the ROM file Example ROM File 80 5B 00 00 7E 00 00 00 7E 00 00 00 7D 02 62 7E 7E 00 00 00 7D 01 EF 7E 91 73 90 FE 90 89 90 14 3D 7F 60 3A 5B 60 3E 7F 3F 00 3D FF 3E CC FF Feedback ...

Page 32: ...d is one byte in length and must always contain a colon The length field is also one byte in length and indicates the number of bytes of data stored in the record Because the length field is one byte in length the maximum amount of data stored in a record is 255 bytes which would require 510 ASCII characters in the HEX file The starting address field indicates the address of the first byte of info...

Page 33: ...he data for this record Because this is an extended linear address record the four characters indicate the value for the upper 16 bits of a 32 bit address Therefore the value of 0x0010 is a 1 MB offset For PSoC microcontroller HEX files the extended linear address is used to offset Flash protection data from the Flash data The Flash pro tection bits start at the 1 MB address data record 1 protecti...

Page 34: ... custom library to this project You then add a project specific MAKE file action to add those project files to a custom library For example a blank project is created for any type of part since interest is only in using C and or assembly the Application Editor and the Debugger The goal for creating a custom library is to cen tralize a set of common functions that can be shared between projects The...

Page 35: ...e this include is the dependencies include project dep if you like project dep that is good include local dep The nice thing about having local dep included at the end of the master Makefile is that the rules used in the Makefile can be redefined see the Help Documentation Supporting Docu ments make pdf for detailed information In this example it is used as an advantage The following shows informa...

Page 36: ... symbol combination is a shortcut syntax that refers to the list of all the targets for example obj o The third argument in the foreach function is expanded into a sequence of commands for each substitution to update or add the object file to the library This local dep example is prepared to han dle both C and assembly source files and put them in the library PSoCToolsLib a The library is cre ated...

Page 37: ...struction The expr string that is used to explain the assembly code format represents the use of assembler direc tives which tell the ImageCraft Assembler how to calculate the constant used in the final machine code Note that in the operation equations the machine code constant is represented by k k1 and k2 While the instruction mnemonics are often shown in all capital letters the ImageCraft Assem...

Page 38: ... ADC A expr 0x09 4 2 ADC A expr 0x0A 6 2 ADC A X expr 0x0B 7 2 ADC expr A 0x0C 7 2 ADC X expr A 0x0D 8 2 ADC expr expr 0x0E 9 3 ADC X expr expr 0x0F 10 3 Conditional Flags CF ZF Set if the sum 255 cleared otherwise Set if the result is zero cleared otherwise Example 1 mov A 0 set accumulator to zero or F 0x02 set carry flag adc A 12 accumulator value is now 13 Example 2 mov 0x39 0 initialize ram 0...

Page 39: ...D expr expr 0x06 9 3 ADD X expr expr 0x07 10 3 ADD SP expr 0x38 5 2 Conditional Flags CF ZF Set if the sum 255 cleared otherwise ADD SP expr does not affect the Carry Flag Set if the result is zero cleared otherwise ADD SP expr does not affect the Zero Flag Example 1 mov A 10 initialize A to 10 decimal add A 240 result is A 250 decimal add A 6 result is A 0 CF 1 ZF 1 Example 2 mov A 10 initialize ...

Page 40: ... result of the logical AND operation If the result of the AND is that all bits are zero the Zero Flag will be set otherwise the Zero Flag Is cleared Note that AND or OR or XOR as appropriate is a read modify write instruction When operating on a register that register must be of the read write type Bitwise AND to a write only register will gener ate nonsense Instructions Operation Opcode Cycles By...

Page 41: ...nt s bit 7 value Set if the result is zero cleared otherwise Example 1 mov A 0x7F initialize A with 127 asl A A 0xFE CF 0 ZF 0 Example 2 mov 0xEB AA initialize RAM 0xEB with 0 asl 0xEB ram 0xEB 54 CF 1 ZF 0 7 4 5 2 3 0 1 CF 0 6 A CF A 7 A 7 A 6 A 6 A 5 A 5 A4 A 4 A 3 A 3 A 2 A 2 A 1 A 1 A 0 A 0 0 ram k CF ram k 7 ram k 7 ram k 6 ram k 6 ram k 5 ram k 5 ram k 4 ram k 4 ram k 3 ram k 3 ram k 2 ram k...

Page 42: ...ample 1 mov A 0x00 initialize A to 0 and F 0x00 make sure all flags are cleared asr A A 0 CF 0 ZF 1 Example 2 mov A 0xFF initialize A to 255 and F 0x00 make sure all flags are cleared asr A A 0xFF CF 1 ZF 0 Example 3 mov A 0xAA initialize A to 170 and F 0x00 make sure all flags are cleared asr A A 0xD5 CF 0 ZF 0 7 4 5 2 3 0 1 6 CF A CF A 0 A 0 A 1 A 1 A 2 A 2 A 3 A 3 A 4 A 4 A 5 A 5 A 6 A 6 A 7 ra...

Page 43: ...d user code will be operating from the same RAM page as before the CALL instruction was executed This instruction has a 12 bit two s complement relative address that is added to the PC The 12 bits are packed into the two byte instruction format by using the lower nibble of the opcode and the sec ond byte of the instruction format Therefore all opcodes with an upper nibble of 9 are CALL instruc tio...

Page 44: ...struction Instructions Operation Opcode Cycles Bytes Mnemonic Argument CMP A expr 0x39 5 2 CMP A expr 0x3A 7 2 CMP A X expr 0x3B 8 2 CMP expr expr 0x3C 8 3 CMP X expr expr 0x3D 9 3 Conditional Flags CF ZF Set if Operand 1 Operand 2 cleared otherwise Set if the operands are equal cleared otherwise Example mov A 34 initialize the accumulator to 34 cmp A 33 A 34 CF cleared A 33 ZF cleared cmp A 34 A ...

Page 45: ...ry Flag is not affected but the Zero Flag will be set if the result of the complement is 0 for example the original value was 0xFF Instructions Operation Opcode Cycles Bytes Mnemonic Argument CPL A 0x73 4 1 Conditional Flags CF ZF Unaffected Set if the result is zero cleared otherwise Example 1 mov A 0xFF cpl A A 0x00 ZF 1 Example 2 mov A 0xA5 cpl A A 0x5A ZF 0 Example 3 mov A 0xFE cpl A A 0x01 ZF...

Page 46: ...e was one the Zero Flag is set Instructions Operation Opcode Cycles Bytes Mnemonic Argument DEC A 0x78 4 1 DEC X 0x79 4 1 DEC expr 0x7A 7 2 DEC X expr 0x7B 8 2 Conditional Flags CF ZF Set if the result is 1 cleared otherwise Set if the result is zero cleared otherwise Example mov 0xEB 3 loop2 The loop will be executed 3 times dec 0xEB jnz loop2 Jump will not be taken when ZF is set by DEC i e wait...

Page 47: ...OR WDR and XRES are all hardware resets that will cause a complete system reset including the resetting of reg isters to their power on state Watchdog reset will not cause the Watchdog Timer to be disabled while all other resets will disable the Watchdog Timer Instructions Operation Opcode Cycles Bytes Mnemonic Argument HALT 0x30 9 1 Conditional Flags CF ZF Unaffected Unaffected Example halt sets ...

Page 48: ... Instructions Operation Opcode Cycles Bytes Mnemonic Argument INC A 0x74 4 1 INC X 0x75 4 1 INC expr 0x76 7 2 INC X expr 0x77 8 2 Conditional Flags CF ZF Set if value after the increment is 0 cleared otherwise Set if the result is zero cleared otherwise Example 1 mov A 0x00 initialize A to 0 or F 0x06 make sure CF and ZF are set 1 inc A A 0x01 CF 0 ZF 0 Example 2 mov A 0xFF initialize A to 0 and F...

Page 49: ...he table is taken as the value of the Accumulator when the INDEX instruction is exe cuted The maximum readable table size is 256 bytes due to the Accumulator being 8 bits in length Instructions Operation Opcode Cycles Bytes Mnemonic Argument INDEX expr 0xFx 13 2 Conditional Flags CF ZF Unaffected Set if the byte returned to A is zero Example 0000 OUT_REG equ 04h 0000 40 04 nop 0001 50 03 04 mov A ...

Page 50: ...ACC instruction uses a two byte instruction format where the lower nibble of the first byte is used for the upper 4 bits of the 12 bit relative address This causes an effective 4 bit opcode Therefore the following are all valid opcode bytes for the JACC instruction 0xE0 0xE1 0xE2 0xEF Instructions Operation Opcode Cycles Bytes Mnemonic Argument JACC expr 0xEx 7 2 Conditional Flags CF ZF Unaffected...

Page 51: ...ction format where the lower nibble of the first byte is used for the upper 4 bits of the 12 bit relative address This causes an effective 4 bit opcode Therefore the following are all valid opcode bytes for the JC instruction 0xC0 0xC1 0xC2 0xCF Instructions Operation Opcode Cycles Bytes Mnemonic Argument JC expr 0xCx 5 2 Conditional Flags CF ZF Unaffected Unaffected Example 0000 _main 0000 55 3C ...

Page 52: ...r nibble of the first byte is used for the upper 4 bits of the 12 bit relative address This causes an effective 4 bit opcode Therefore the following are all valid opcode bytes for the JMP instruction 0x80 0x81 0x82 0x8F Instructions Operation Opcode Cycles Bytes Mnemonic Argument JMP expr 0x8x 5 2 Conditional Flags CF ZF Unaffected Unaffected Example 0000 _main 0000 80 01 05 jmp SubFun Jump is for...

Page 53: ...tion format where the lower nibble of the first byte is used for the upper 4 bits of the 12 bit relative address This causes an effective 4 bit opcode Therefore the following are all valid opcode bytes for the JNC instruction 0xD0 0xD1 0xD2 0xDF Instructions Operation Opcode Cycles Bytes Mnemonic Argument JNC expr 0xDx 5 2 Conditional Flags CF ZF Unaffected Unaffected Example 0000 _main 0000 55 3C...

Page 54: ...ruction format where the lower nibble of the first byte is used for the upper 4 bits of the 12 bit relative address This causes an effective 4 bit opcode Therefore the following are all valid opcode bytes for the JNZ instruction 0xB0 0xB1 0xB2 0xBF Instructions Operation Opcode Cycles Bytes Mnemonic Argument JNZ expr 0xBx 5 2 Conditional Flags CF ZF Unaffected Unaffected Example 0000 _main 0000 55...

Page 55: ...ion format where the lower nibble of the first byte is used for the upper 4 bits of the 12 bit relative address This causes an effective 4 bit opcode Therefore the following are all valid opcode bytes for the JZ instruction 0xA0 0xA1 0xA2 0xAF Instructions Operation Opcode Cycles Bytes Mnemonic Argument JZ expr 0xAx 5 2 Conditional Flags CF ZF Unaffected Unaffected Example 0000 _main 0000 55 3C 02...

Page 56: ...lly selects the stack page as the destination for the push during the LCALL instruc tion Therefore a LCALL instruction may be issued in any RAM page After the LCALL instruction has completed user code will be operating from the same RAM page as before the LCALL instruc tion was executed This instruction has a 16 bit unsigned address A three byte instruction format is used where the first byte is a...

Page 57: ... expr 0x7D 7 3 Conditional Flags CF ZF Unaffected Unaffected Example 0000 _main 0000 7D 00 03 07 ljmp SubFun Although in this example a full 16 bit address is not needed for the jump to SubFun the listing above shows that the ljmp instruction is using a three byte format which accommodates the 16 bit absolute jump address of 0x0003 0003 0003 SubFun 0003 7D 00 00 07 ljmp _main Note that this instru...

Page 58: ...7 4 2 MOV X expr 0x58 6 2 MOV X X expr 0x59 7 2 MOV expr X 0x5A 5 2 MOV A X 0x5B 4 1 MOV X A 0x5C 4 1 MOV A reg expr 0x5D 6 2 MOV A reg X expr 0x5E 7 2 MOV expr expr 0x5F 10 3 MOV REG expr A 0x60 5 2 MOV REG X expr A 0x61 6 2 MOV REG expr expr 0x62 8 3 MOV REG X expr expr 0x63 9 3 Conditional Flags CF ZF Unaffected Set if A is the destination and the result is zero Example mov A 0x01 accumulator w...

Page 59: ...ode Cycles Bytes Mnemonic Argument MVI A expr 0x3E 10 2 MVI expr A 0x3F 10 2 Conditional Flags CF ZF Unaffected Set if A is updated with zero Example 1 mov 10h 4 mov 11h 3 mov EBh 10h initialize MVI read pointer to 10h mvi A EBh A 4 ram EBh 11h mvi A EBh A 3 ram EBh 12h Example 2 mov EBh 10h initialize MVI write pointer to 10h mov A 8 mvi EBh A ram 10h 8 ram EBh 11h mov A 1 mvi EBh A ram 11h 1 ram...

Page 60: ...B M8C Instruction Set 4 23 No Operation NOP Performs no operation but consumes 4 CPU clock cycles This is a one byte instruction Instructions Operation Opcode Cycles Bytes Mnemonic Argument NOP None 0x40 4 1 Conditional Flags CF ZF Unaffected Unaffected Feedback ...

Page 61: ...set or cleared based on the result of the logical OR operation If the result of the OR instruction is that all bits are zero the Zero Flag will be set other wise the Zero Flag is cleared Note that OR or AND or XOR as appropriate is a read modify write instruction When operating on a register that register must be of the read write type Bitwise OR to a write only register will gener ate nonsense In...

Page 62: ...ically selects the stack page as the source for the memory read during the POP instruction Therefore a POP instruction may be issued in any RAM page After the POP instruction has completed user code will be operating from the same RAM page as before the POP instruction was executed See the RAM Paging chapter of the PSoC Technical Reference Manual TRM for details Instructions Operation Opcode Cycle...

Page 63: ...esig nated stack page defined by the value of the STK_PP Register The M8C automatically selects the stack page as the source for the memory write during the PUSH instruction Therefore a PUSH instruction may be issued in any PUSH page After the PUSH instruction has completed user code will be operating from the same RAM page as before the PUSH instruction was executed See the RAM Paging chapter of ...

Page 64: ...he M8C automatically selects the stack page as the source for the pop during the RET instruction Therefore a RET instruction may be issued in any RAM page After the RET instruction has completed user code will be operating from the same RAM page as before the RET instruction was executed See the RAM Paging chapter of the PSoC Technical Reference Manual TRM for details Instructions Operation Opcode...

Page 65: ... Flags are updated with the values from the first byte popped off the stack For PSoC devices with more than 256 bytes of RAM the stack is confined to a single designated stack page defined by the value of the STK_PP Register The M8C automatically selects the stack page as the source for the pop during the RETI instruction Therefore an RETI instruction may be issued in any RAM page After the RETI i...

Page 66: ...F ZF Set if the MSB of the specified operand was set before the shift cleared otherwise Set if the result is zero cleared otherwise Example and F 0xFB clear carry flag mov A 0x7F initialize A with 127 rlc A A 0xFE CF 0 ZF 0 7 4 5 2 3 0 1 6 CF A CF A 7 A 7 A 6 A 6 A 5 A 5 A4 A 4 A 3 A 3 A 2 A 2 A 1 A 1 A 0 A 0 CF ram k CF ram k 7 ram k 7 ram k 6 ram k 6 ram k 5 ram k 5 ram k 4 ram k 4 ram k 3 ram k...

Page 67: ...if the retrieved byte is zero otherwise the Zero Flag is cleared The Carry Flag is not affected by this instruction Instructions Operation Opcode Cycles Bytes Mnemonic Argument ROMX 0x28 11 1 Conditional Flags CF ZF Unaffected Set if A is zero cleared otherwise Example 0000 _main 0000 50 00 04 mov A 00h 0002 57 08 04 mov X 08h 0004 28 11 romx 0005 60 00 05 mov reg 00h A 0007 40 04 nop 0008 30 04 h...

Page 68: ...eared otherwise Example 1 or F 0x04 set carry flag and A 0x00 clear the accumulator rrc A A 0x80 CF 0 ZF 0 Example 2 and F 0xFB clear carry flag mov A 0xFF initialize A to 255 and A 0x00 make sure all flags are cleared rrc A A 0x7F CF 1 ZF 0 Example 3 or F 0x04 set carry flag mov 0xEB 0xAA initialize A to 170 rrc 0xEB ram 0xEB 0xD5 CF 1 ZF 0 7 4 5 2 3 0 1 6 CF A CF A 0 A 0 A 1 A 1 A 2 A 2 A 3 A 3 ...

Page 69: ...es Mnemonic Argument SBB A expr 0x19 4 2 SBB A expr 0x1A 6 2 SBB A X expr 0x1B 7 2 SBB expr A 0x1C 7 2 SBB X expr A 0x1D 8 2 SBB expr expr 0x1E 9 3 SBB X expr expr 0x1F 10 3 Conditional Flags CF ZF Set if treating the numbers as unsigned the difference 0 cleared other wise Set if the result is zero cleared otherwise Example 1 mov A 0 set accumulator to zero or F 0x02 set carry flag sbb A 12 accumu...

Page 70: ...ic Argument SUB A expr 0x11 4 2 SUB A expr 0x12 6 2 SUB A X expr 0x13 7 2 SUB expr A 0x14 7 2 SUB X expr A 0x15 8 2 SUB expr expr 0x16 9 3 SUB X expr expr 0x17 10 3 Conditional Flags CF ZF Set if treating the numbers as unsigned the difference 0 cleared other wise Set if the result is zero cleared otherwise Example 1 mov A 0 set accumulator to zero or F 0x04 set carry flag sub A 12 accumulator val...

Page 71: ...lag is cleared The swap X expr instruction does not affect either the Carry or Zero Flags Instructions Operation Opcode Cycles Bytes Mnemonic Argument SWAP A X 0x4B 5 1 SWAP A expr 0x4C 7 2 SWAP X expr 0x4D 7 2 SWAP A SP 0x4E 5 1 Conditional Flags CF ZF Unaffected Set if Accumulator is cleared Example mov A 0x30 swap A SP SP 0x30 A equals previous SP value t X X A A t t ram k ram k A A t t ram k r...

Page 72: ...ilable supervisory routines Instructions Operation Opcode Cycles Bytes Mnemonic Argument SSC 0x00 15 1 Conditional Flags CF ZF Unaffected Unaffected Example The following example is one way to set up an SSC operation for the CY8C25xxx and CY8C26xxx PSoC devices PSoC Designer uses the signature created by the following lines of code to recognize supervisory system calls and configures the In Circui...

Page 73: ...ry Flag is not affected by the TST instruction Instructions Operation Opcode Cycles Bytes Mnemonic Argument TST expr expr 0x47 8 3 TST X expr expr 0x48 9 3 TST REG expr expr 0x49 9 3 TST REG X expr expr 0x4A 10 3 Conditional Flags CF ZF Unaffected Set if the result of AND is zero cleared otherwise Example mov 0x00 0x03 tst 0x00 0x02 CF 0 ZF 0 i e bit 1 is 1 tst 0x00 0x01 CF 0 ZF 0 i e bit 0 is 1 t...

Page 74: ...ation If the result of the XOR instruction is that all bits are zero the Zero Flag will be set otherwise the Zero Flag is cleared The Carry Flag is not affected Note that XOR or AND or OR as appropriate is a read modify write instruction When operating on a register that register must be of the read write type Bitwise XOR to a write only register will gener ate nonsense Instructions Operation Opco...

Page 75: ...onics However the ImageCraft Assembler does consider case for user defined symbols i e labels Table 5 1 presents a summary of the assembler directives Table 5 1 ImageCraft Assembler Directives Summary Symbol Directive AREA Area ASCIZ NULL Terminated ASCII String BLK RAM Byte Block BLKW RAM Word Block DB Define Byte DF Define Floating point Number DS Define ASCII String DSU Define UNICODE String DW...

Page 76: ... are always overlay AREAs ROM Specifies that code or data is stored in Flash ABS Absolute i e non relocatable location for code or data specified by the ORG directive Default value of AREAs for type ABS or REL directives is not specified REL Allows the Linker to relocate the code or data CON Specifies that sequential AREAs follow each other in memory Each AREA is allocated its own memory The total...

Page 77: ...changes the UserModules Area you cannot call routines in this area from a code area created with AREA direc tive using a name other than text All normal user code that is to be compressed must be in the default text area If you create code in other areas for example in a bootloader then it must not call any functions in the text area How ever it is acceptable for a function in the text area to cal...

Page 78: ...th quotation marks The string is stored character by character in ASCII HEX format The backslash character is used in the string as an escape character Non printing characters such as n and r can be used A quo tation mark can be entered into a string using the backslash a single quote as and a backslash as Directive Arguments ASCIZ character string Example My String is defined with a terminating N...

Page 79: ... an expression specifying the size of the block in bytes to reserve The AREA directive must be used to ensure the block of bytes will reside in the cor rect memory location PSoC Designer requires that the AREA bss be used for RAM variables Directive Arguments BLK size Example A 4 byte variable called MyVariable is allocated AREA bss MyVariable BLK 4 Feedback ...

Page 80: ...ck of RAM The amount of RAM reserved is determined by the size argument to the directive The units for the size argument is words 16 bits PSoC Designer requires that the AREA bss be used for RAM variables Directive Arguments BLKW size Example A 4 byte variable called MyVariable is allocated AREA bss MyVariable BLKW 2 Feedback ...

Page 81: ...lues to the reserved bytes This directive is useful for creating data tables in ROM Arguments may be constants or labels The length of the source line limits the number of arguments in a DB directive Directive Arguments DB value1 value2 valuen Example 3 bytes are defined starting at address 3000 MyNum EQU 77h ORG 3000h MyTable DB 55h 66h MyNum Feedback ...

Page 82: ...specified values to each reserved pair The format used is the IEEE 754 Single Format stored in big endian format This directive is useful for creating data tables in ROM Arguments must be constants Only the length of the source line limits the number of arguments in a DF directive Directive Arguments DF value1 value2 valuen Example MyTable DF 1 2345 1 07e 03f Feedback ...

Page 83: ...EX format The backslash character is used in the string as an escape character Non printing characters such as n and r can be used A quo tation mark can be entered into a string using the backslash a single quote as and a backslash as The string is not null terminated To create a null terminated string follow the DS directive with a DB 00h or use ASCIZ directive Directive Arguments DS character st...

Page 84: ...er by character in UNICODE format Each character in the string is stored with the low byte followed by the high byte The backslash character is used in the string as an escape character Non printing characters such as n and r can be used A quotation mark can be entered into a string using the backslash a single quote as and a backslash as Directive Arguments DSU character string Example My String ...

Page 85: ...ecified words to each reserved byte This direc tive is useful for creating tables in ROM The arguments may be constants or labels Only the length of the source line limits the number of arguments in a DW directive Directive Arguments DW value1 value2 valuen Example 6 bytes are defined starting at address 2000 MyNum EQU 3333h ORG 2000h MyTable DW 1111h 2222h MyNum Feedback ...

Page 86: ...he specified words to each reserved byte swapping the order of the upper and lower bytes The arguments may be constants or labels The length of the source line limits the number of argu ments in a DWL directive Directive Arguments DWL value1 value2 valuen Example 6 bytes are defined starting at address 2000 MyNum EQU 6655h ORG 2000h MyTable DWL 2211h 4433h MyNum Feedback ...

Page 87: ... may have only one argument and if a label is defined more than once an assembly error will occur To use the same equate in more than one assembly source file place the equate in an inc file and include that file in the referencing source files Do not export equates from assembly source files or the PSoC Designer Linker will resolve the directive in unpredictable ways Directive Arguments EQU label...

Page 88: ...ates that a label is global and can be referenced in another file Otherwise the label is not vis ible to another file Another way to export a label is to end the label definition with two colons instead of one Directive Arguments EXPORT EXPORT label Example Export MyVariable AREA bss MyVariable BLK 1 Feedback ...

Page 89: ...atements can be nested ELSE delineates a not true action for a previous IF directive ENDIF finishes a section of conditional assembly that began with an IF directive Directive Arguments IF ELSE ENDIF value Example Sections of the source code are conditional Cond1 EQU 1 Cond2 EQU 0 ORG 1000h IF Cond1 ADD A 33h IF Cond2 ADD A FFh ENDIF Cond1 NOP Cond1 ELSE MOV A FFh ENDIF Cond2 The example creates t...

Page 90: ... encountered or the end of file is reached If additional INCLUDE directives are encountered additional source files are read in When an end of file is encountered the Assembler resumes reading the previous file Specify the full or relative path to the file if the source file does not reside in the current directory Directive Arguments INCLUDE file name Example Three files are included into the sou...

Page 91: ...directives For the code compressor to function all data defined in ROM with the ASCIZ DB DS DSU DW or DWL directives must use this directive The LITERAL directive must be followed by an exported global label The ENDLITERAL directive resumes code compression Directive Arguments LITERAL ENDLITERAL none Example Code compression is suspended for the data table Export DataTable LITERAL DataTable DB 01h...

Page 92: ...nding value from the macro call Any assembly statement is allowed in a macro body except for another macro statement and labels that are referenced from outside the macro Labels in macros have to be local to each invocation of the macro for example macro xyz mov a 2 loop mov a x jnz loop endmacro Within a macro body the expression digit where digit is between 0 and 9 is replaced by the cor respond...

Page 93: ... define directives DB DS and DW The ORG directive can only be used in areas with the ABS mode An operand is required for an ORG directive and may be an integer constant a label or the cur rent PC The ImageCraft Assembler does not keep track of areas previously defined and will not flag overlapping areas in a single source file Directive Arguments ORG address Example The bytes defined after the ORG...

Page 94: ...D SP 0 Used to prevent code compression of the code between the OR F 0 and ADD SP 0 instructions The code compressor may need to be suspended for timing loops and jump tables If the JACC instruction is used to access fixed offset boundaries in a jump table any LJMP and or LCALL instruc tion entries in the table may be optimized to relative jumps or calls changing the proper offset value for the JA...

Page 95: ...ImageCraft Assembly Language Guide Document 001 44475 Rev B 95 Assembler Directives Feedback ...

Page 96: ...96 ImageCraft Assembly Language Guide Document 001 44475 Rev B Assembler Directives Feedback ...

Page 97: ... PSoC Designer when a project build is executed The linker can also take input from a library which is basically a file containing multiple object files In producing the output file the Linker resolves any references between the input files In some detail the linking steps involve 1 Making the startup file boot asm the first file to be linked The startup file initializes the execution environment ...

Page 98: ... cfm or www cypress com and click on Technical and Support KnowledgeBase at the bottom of the page Possible Causes 1 The label in a LITERAL or SECTION segment of code has not been made global using the EXPORT directive or a double colon 2 A LITERAL segment has only a label and no defined data a SECTION was not followed by a label b LITERAL was not followed by a label c ENDSECTION has no matching S...

Page 99: ...A 1 Assembly Syntax Expressions Precedence Expression Symbol Form 1 Bitwise Complement a 2 Multiplication Division Modulo a b a b a b 3 Addition Subtraction a b a b 4 Bitwise AND a b 5 Bitwise XOR a b 6 Bitwise OR a b 7 High Byte of an Address a 8 Low Byte of an Address a Table A 2 Constants Formats Radix Name Formats Example 127 ASCII Character J mov A J character constant mov A use to escape mov...

Page 100: ...ICODE String DW Define Word DWL Define Word With Little Endian Ordering ELSE Alternative Result of IF Directive ENDIF End Conditional Assembly ENDM End Macro EQU Equate Label to Variable Value EXPORT Export IF Start Conditional Assembly INCLUDE Include Source File LITERAL ENDLITERAL Prevent Code Compression of Data MACRO Start Macro Definition ORG Area Origin SECTION ENDSECTION Section for Dead Co...

Page 101: ... 2C 054 76 4C 114 L 108 6C 154 l 13 0D 015 CR 45 2D 055 77 4D 115 M 109 6D 155 m 14 0E 016 SO 46 2E 056 78 4E 116 N 110 6E 156 n 15 0F 017 SI 47 2F 057 79 4F 117 O 111 6F 157 o 16 10 020 DLE 48 30 060 0 80 50 120 P 112 70 160 p 17 11 021 DC1 49 31 061 1 81 51 121 Q 113 71 161 q 18 12 022 DC2 50 32 062 2 82 52 122 R 114 72 162 r 19 13 023 DC3 51 33 063 3 83 53 123 S 115 73 163 s 20 14 024 DC4 52 34...

Page 102: ... 4 1 RRC A C Z 14 7 2 SUB expr A C Z 41 9 3 AND reg expr expr Z 6E 7 2 RRC expr C Z 15 8 2 SUB X expr A C Z 42 10 3 AND reg X expr expr Z 6F 8 2 RRC X expr C Z 16 9 3 SUB expr expr C Z 43 9 3 OR reg expr expr Z 70 4 2 AND F expr C Z 17 10 3 SUB X expr expr C Z 44 10 3 OR reg X expr expr Z 71 4 2 OR F expr C Z 18 5 1 POP A Z 45 9 3 XOR reg expr expr Z 72 4 2 XOR F expr C Z 19 4 2 SBB A expr C Z 46 ...

Page 103: ...A expr C Z 70 4 2 AND F expr C Z 5A 5 2 MOV expr X 12 6 2 SUB A expr C Z 41 9 3 AND reg expr expr Z 5B 4 1 MOV A X Z 13 7 2 SUB A X expr C Z 42 10 3 AND reg X expr expr Z 5C 4 1 MOV X A 14 7 2 SUB expr A C Z 64 4 1 ASL A C Z 5D 6 2 MOV A reg expr Z 15 8 2 SUB X expr A C Z 65 7 2 ASL expr C Z 5E 7 2 MOV A reg X expr Z 16 9 3 SUB expr expr C Z 66 8 2 ASL X expr C Z 5F 10 3 MOV expr expr 17 10 3 SUB ...

Page 104: ...104 ImageCraft Assembly Language Guide Document 001 44475 Rev B Feedback ...

Page 105: ...uction 43 CMP instruction 44 compiling file into library module 34 compiling source files 97 complement accumulator instruction 45 components of assembly source file 25 compressor and dead code error message elimination 98 conditional source directive 89 constants format table 99 conventions 8 CPL instruction 45 CPU core addressing modes 18 instruction formats 16 instruction set summary 14 15 102 ...

Page 106: ... instruction 53 jump if not zero instruction 54 jump if zero instruction 55 jump instruction 52 JZ instruction 55 L LCALL instruction 56 library module compiling file 34 linker operations 97 listing file format 30 LITERAL directive 91 LJMP instruction 57 local labels 26 long call instruction 56 long jump instruction 57 M M8C microprocessor 11 address spaces 12 addressing modes 18 instruction forma...

Page 107: ...7 rotate left through carry instruction 66 rotate right through carry instruction 68 RRC instruction 68 S SBB instruction 69 SECTION directive 94 section for dead code elimination directive 94 source file components comments 29 directives 30 labels 26 mnemonics 27 operands 28 source file format 25 source instructions direct 19 immediate 18 indexed 19 indirect post increment 22 SSC instruction 72 S...

Page 108: ...108 ImageCraft Assembly Language Guide Document 001 44475 Rev B Index Feedback ...

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