38
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Supervisory ROM (SROM)
about 1 ms longer than WriteBlock (but still within the Twrite
spec). The function performs a three-step process. In the
first step, 128 bytes of data are moved from SRAM to the
Flash. In the second step, Flash is programmed with the
data. In the final step the Flash data are compared against
the input data values, thus verifying that the write was suc-
cessful. The write and verify is one SROM operation; there-
fore, the SROM is not exited until the verify is completed.
The parameters for this block are identical to the WriteBlock
(see
WriteBlock Function on page 35
). If the verify operation
fails, the 0x04 error code is returned at SRAM address 0xF8
3.1.2.12
HWBootReset Function
The HWBootReset function is used to force a hardware
reset. A hardware reset causes all registers to go back to
their POR state. Then, the SROM SWBootReset function
executes, followed by Flash code execution beginning at
address 0x0000.
The HWBootReset function only requires that the CPU_A,
KEY1, and KEY2 be set up correctly. As with all other
SROM functions, if the setup is incorrect, the SROM exe-
cutes a
HALT
. Then, either a POR, XRES, or WDR is
needed to clear the
HALT
.
See Chapter “System Resets” on
for more information.
3.2
Register Definitions
This chapter has no register detail information because
there are no registers directly assigned to the Supervisory
ROM.
Table 3-18. WriteAndVerify Parameters (0Ah)
Name
Address
Type
Description
KEY1
0,F8h
RAM
3Ah.
KEY2
0,F9h
RAM
Stack Pointer value+3, when
SSC
is
executed.
BLOCKID
0,FAh
RAM
Flash block number.
POINTER
0,FBh
RAM
First of 128 addresses in SRAM, where
the data to be stored in Flash, is located
before calling WriteBlock.
Table 3-19. HWBootReset Parameters (0Fh)
Name
Address
Type
Description
KEY1
0,F8h
RAM
3Ah.
KEY2
0,F9h
RAM
Stack Pointer value+3, when
SSC
is executed.
Summary of Contents for PSoC CY8CTMG20 Series
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