Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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168 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Full-Speed USB
For a USB IN transaction, the USB SIE is reading data from
the PMA and sending the data to the USB host. The follow-
ing steps must be used to set up a PMA channel for a USB
IN transaction. These steps assume that the data has
already been written by the M8C into the dedicated USB
SRAM.
1. Select the PMA channel whose number matches the
endpoint number that is handling the IN transaction.
2. Write the PMA channel's PMAx_RA register with the
address of the first byte in SRAM that is used for the IN
transaction.
3. Configure the USB endpoint registers with the proper
byte count and enable the endpoint to send data when
the IN transaction occurs.
Because the PMA prefetches data for M8C and USB SIE
reads, step two above is very important. This step not only
sets the first address from which data is read by the USB
SIE; but, it also triggers a read operation on the dedicated
USB SRAM and stores the result of that read in the
PMAx_DR ready for the USB SIE to read. When the USB
SIE begins the IN transaction for the endpoint, it uses its
byte counter to tell the PMA which byte is needed next.
Therefore, when the first byte of the transaction is read by
the SIE, the PMA automatically fetches the next byte in
preparation for the USB SIEs next byte request.
For a USB OUT transaction, the USB SIE is writing data to
the PMA that was received from the USB host. The following
steps must be used to set up a PMA channel for a USB OUT
transaction.
1. Select the PMA channel whose number matches the
endpoint number that is handling the OUT transaction.
2. Write the PMA channel's PMAx_WA register with the
address of the first byte in SRAM that is used for the
OUT transaction.
3. Configure the USB endpoint with the proper maximum
receive byte count and enable the endpoint to receive
the OUT transaction.
As with the IN transaction, the PMA uses the byte counter
from the SIE as an offset to the value of the PMAx_WA reg-
ister. As the USB SIE sends bytes to the PMA, the counter is
added to the base address and the data byte is written into
the dedicated USB SRAM. Should an error occur in the OUT
transaction and the packet be resent by the USB host, the
byte count is reset to zero and the PMA writes the new data
over top of the potentially corrupt data from the previous
failed transaction.
If the number of bytes received exceeds the count in the
endpoint's count register, the extra bytes are not written into
the USB SRAM, but the received byte count reported in the
endpoint count registers includes the ignored bytes.
20.2.3 Oscillator Lock
The PSoC device can operate without using any external
components, such as a crystal, and still achieve the clock
accuracy required for full-speed USB. It does this by locking
its internal oscillator to the incoming USB traffic. Therefore,
the initial accuracy of the oscillator may not meet the
required accuracy (
±
0.25%), but it self-tunes to this preci-
sion before the device needs to transmit USB data.
This oscillator locking feature is disabled by default and
must be enabled by firmware. In USB systems, this feature
must always be enabled unless the device is being used
with an accurate external clock. The EnableLock bit in the
USB_CR1 register is used to turn on the locking feature.
20.2.4 Transceiver
The internal USB transceiver interfaces to the external USB
bus to transmit and receive signals according to the USB 2.0
Specification. In normal USB operation, the transceiver
interfaces directly to the SIE and no user interaction is
needed after initialization. The USB Enable bit in the
USB_CR0 register must be set to enable the transceiver for
USB operation. The I/O Mode bit in USBIO_CR1 must not
be set during normal USB mode of operation. The trans-
ceiver can also be used in non-USB modes, since the D+
and D- pins can be read and written through register control
bits. This enables multi-purpose use of these pins (for exam-
ple, in a system that supports both USB and PS/2 signaling).
Clearing the USB Enable bit of USB_CR0 powers down the
USB differential receiver and disables USB communication.
For USB operation, the transceiver contains an internal 1.5
k
Ω
pull up resistor on the D+ line. This resistor is isolated
from the D+ pin at reset and is attached under firmware con-
trol through the USBPUEN bit in the USBIO_CR1 register.
After the D+ pull up resistor is connected to the D+ line, the
system normally detects that as an attach and begins the
USB enumeration process. No additional external pull up
resistor must be added to the D+ line, since the transceiver
signaling is optimized for use with the internal D+ pull up
resistor. However, low value series resistors (24
Ω
) must be
added externally to meet the driving impedance requirement
for full-speed USB.
The transceiver also includes 5 k
Ω
pull up resistors on both
the D+ and D- pins for communication at PS/2 or similar sig-
naling levels. These resistors are disconnected at reset and
can be connected with the PS2PUEN bit in the USBIO_CR1
register. The D+ and D- pins can also be driven individually
high and low in both USB and non-USB modes. The state of
those pins can be read in any mode. Refer to the description
of the
USBIO_CR0 and USBIO_CR1 registers for more
detail.
20.2.5 USB Suspend
Loss of USB activity, while the USB VBus is still asserted,
indicates that the device must enter USB Suspend mode.
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