Cypress PSoC 6 MCU, Manual

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PSoC 6 MCU Voice Recorder
www.cypress.com
Document Number: 002-22221 Rev. *C 5
Component Instance Name Purpose Non-default Settings
DMA DMA_PlayRight
Transfer data from SRAM to I2S TX
FIFO (right channel)
Trigger Input/Output are checked
See Figure 8
I2S I2S Interface the audio codec See Figure 9
SCB (I2C Master) CodecI2CM Configure the audio codec Mode: Master
CapSense CapSense Scan capacitive buttons and a slider See Figure 10 to Figure 13
GraphicLCDIntf GraphicLCDIntf Interface the TFT LCD Display Bus Width: 8 bit
Interrupt DMA_PDM_IRQ Track the recording transfers
Interrupt DMA_I2S_IRQ Track the playing transfers
Clock Clk_HF4 Master clock for the audio codec
Clock Clock_Graphics Clock for GraphicLCDIntf
Digital Input Pin PDM_DATA PDM Data input
Digital Output Pin PDM_CLK PDM Clock output
Digital Output Pin TX_SDO I2S TX Data output
Digital Output Pin TX_SCK I2S TX Clock output
Digital Output Pin TX_WS I2S TX Word Select output
Digital Output Pin Pin_d_c Data/Command signal for the LCD
Digital Output Pin Pin_ncs Active-LOW chip select for the LCD
Digital Output Pin Pin_nwr
Active-LOW write control signal for
LCD
Digital Output Pin Pin_nrd
Active-LOW read control signal for
LCD
Digital Output Pin Intf_nreset Active-LOW reset signal for the LCD HW Connection is Unchecked
Bidirectional Pin Pin_LSB 8-bit pin bus for the LCD Number of pins: 8
Digital Output Pin RED_LED Assert when an error is detected
Initial drive state: High
HW Connection is Unchecked
For information on the hardware resources used by a Component, see the Component datasheet.
Figure 4 through Figure 10 highlight the non-default settings for each Component in this example.