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Document Number: 002-02521 Rev. *F 

Page 22 of 39

CYBLE-012011-00

CYBLE-012012-10

Serial Communication

Table 28.  Fixed I

2

C DC Specifications

Table 30.  Fixed UART DC Specifications

Table 31.  Fixed UART AC Specifications

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

I

I2C1

Block current consumption at 100 kHz

50

µA

I

I2C2

Block current consumption at 400 kHz

155

µA

I

I2C3

Block current consumption at 1 Mbps

390

µA

I

I2C4

I

2

C enabled in Deep-Sleep mode

1.4

µA

Table 29.  Fixed I

2

C AC Specifications

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

F

I2C1

Bit rate

400

kHz

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

I

UART1

Block current consumption at 100 kbps

55

µA

I

UART2

Block current consumption at 1000 kbps

312

µA

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

F

UART

Bit rate

1

Mbps

Table 32.  Fixed SPI DC Specifications

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

I

SPI1

Block current consumption at 1 Mbps

360

µA

I

SPI2

Block current consumption at 4 Mbps

560

µA

I

SPI3

Block current consumption at 8 Mbps

600

µA

Table 33.  Fixed SPI AC Specifications

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

F

SPI

SPI operating frequency (master; 6x 
over sampling)

8

MHz

Table 34.  Fixed SPI Master Mode AC Specifications

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

T

DMO

MOSI valid after SCLK driving edge

18

ns

T

DSI

MISO valid before SCLK capturing edge 
Full clock, late MISO sampling used

20

– 

ns

Full clock, late MISO sampling

T

HMO

Previous MOSI data hold time 

0

ns

Referred to Slave capturing edge

Table 35.  Fixed SPI Slave Mode AC Specifications

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

T

DMI

MOSI valid before SCLK capturing edge

40

– 

ns

T

DSO

MISO valid after SCLK driving edge

– 

– 

42 + 3 × 

T

CPU

ns

T

DSO_ext

MISO Valid after SCLK driving edge in 
external clock mode. V

DD

 < 3.0 V

50

ns

Summary of Contents for EZ-BLE PRoC CYBL11172-56LQXI

Page 1: ...ating at up to 48 MHz Watchdog timer with dedicated internal low speed oscillator ILO Two pin SWD for programming Power Consumption TX output power 18 dbm to 3 dbm Received signal strength indicator RSSI with 1 dB resolution TX current consumption of 15 6 mA radio only 0 dbm RX current consumption of 16 4 mA radio only Low power mode support Deep Sleep 1 3 µA with watch crystal oscillator WCO on H...

Page 2: ...ntegrated Design Environment IDE that enables concurrent hardware and firmware editing compiling and debugging of PSoC 3 PSoC 4 PSoC 5LP PSoC 4 BLE PRoC BLE and EZ BLE module systems with no code size limitations PSoC peripherals are designed using schematic capture and simple graphical user interface GUI with over 120 pre verified production ready PSoC Components PSoC Components are analog and di...

Page 3: ...20 Serial Communication 22 Memory 23 System Resources 23 Environmental Specifications 29 Environmental Compliance 29 RF Certification 29 Safety Certification 29 Environmental Conditions 29 ESD and EMI Protection 29 Regulatory Information 30 FCC 30 Industry Canada IC Certification 31 European R TTE Declaration of Conformity 31 MIC Japan 32 KC Korea 32 Packaging 33 Ordering Information 35 Part Numbe...

Page 4: ...d within the physical dimensions shown in the mechanical drawings in Figure 1 All dimensions are in millimeters mm Table 1 Module Design Dimensions See Figure 1 on page 5 for the mechanical reference drawing for CYBLE 01201X X0 Dimension Item Specification Module dimensions Length X 14 52 0 15 mm Width Y 19 20 0 15 mm Antenna location dimensions Length X 11 00 0 15 mm Width Y 5 00 0 15 mm PCB thic...

Page 5: ...e Mechanical Drawing Top View Bottom View Side View Note 1 No metal should be located beneath or above the antenna area Only bare PCB material should be located beneath the antenna area For more information on recommended host PCB layout see Figure 3 Figure 4 Figure 5 and Figure 6 and Table 3 ...

Page 6: ...d at the far corner This placement minimizes the additional recommended keep out area stated in item 2 Refer to AN96841 for module placement best practices 2 To maximize RF performance the area immediately around the Cypress BLE module trace antenna should contain an additional keep out area where no grounding or signal trace are contained The keep out area applies to all layers of the host board ...

Page 7: ...imeters unless otherwise noted Pad length of 1 27 mm 0 635 mm from center of the pad on either side shown in Figure 6 is the minimum recommended host pad length The host PCB layout pattern can be completed using either Figure 4 Figure 5 or Figure 6 It is not necessary to use all figures to complete the host PCB layout pattern Figure 4 Host Layout Pattern for CYBLE 01201X X0 Figure 5 Module Pad Loc...

Page 8: ... 13 6 0 39 11 23 15 35 442 13 7 0 39 12 50 15 35 492 13 8 0 39 13 77 15 35 542 13 9 0 39 15 04 15 35 592 13 10 0 39 16 31 15 35 642 13 11 0 39 17 58 15 35 692 13 12 2 04 18 82 80 31 740 94 13 3 31 18 82 130 31 740 94 14 4 58 18 82 180 31 740 94 15 5 85 18 82 230 31 740 94 16 7 12 18 82 280 31 740 94 17 8 39 18 82 330 31 740 94 18 9 66 18 82 380 31 740 94 19 10 93 18 82 430 31 740 94 20 12 20 18 82...

Page 9: ...RX SCB0_MOSI SCB0_SDA TCPWM Sensor 20 P1 0 TCPWM Sensor 21 P0 4 SCB0_RX SCB0_MOSI SCB0_SDA TCPWM Sensor 22 P0 5 SCB0_TX SCB0_MISO SCB0_SCL TCPWM Sensor 23 P0 7 SCB0_CTS SCB0_SCLK TCPWM Sensor SWDCLK 24 P0 6 SCB0_RTS SCB0_SS0 TCPWM Sensor SWDIO 25 GND 5 Ground Connection 26 GND 5 Ground Connection 27 GND 5 Ground Connection 28 GND 5 Ground Connection 29 VDDR Radio Power Supply 1 9V to 5 5V 30 P5 0 ...

Page 10: ...ion options are available for any application 1 Single supply Connect VDD and VDDR to the same supply 2 Independent supply Power VDD and VDDR separately External Component Recommendation In either connection scenario it is recommended to place an external ferrite bead between the supply and the module connection The ferrite bead should be positioned as close as possible to the module pin connectio...

Page 11: ...Document Number 002 02521 Rev F Page 11 of 39 CYBLE 012011 00 CYBLE 012012 10 Figure 8 Recommended Host Schematic for an Independent Supply Option Independent Power Supply Option Seen from Bottom ...

Page 12: ...Document Number 002 02521 Rev F Page 12 of 39 CYBLE 012011 00 CYBLE 012012 10 The CYBLE 01201X X0 schematic is shown in Figure 9 Figure 9 CYBLE 01201X X0 Schematic Diagram ...

Page 13: ... Table 6 details trace antenna used in the CYBLE 01201X X0 module For more information see Table 8 Table 6 Trace Antenna Specifications Component Reference Designator Description Silicon U1 56 pin QFN Programmable Radio on Chip PRoC with BLE Crystal Y1 24 000 MHz 12PF Crystal Y2 32 768 kHz 12 5PF Item Description Frequency Range 2400 2500 MHz Peak Gain 0 5 dBi typical Average Gain 0 5 dBi typical ...

Page 14: ... IGPIO_ABS Maximum current per GPIO 25 25 mA Absolute maximum IGPIO_injection GPIO injection current Maximum for VIH VDD and minimum for VIL VSS 0 5 0 5 mA Absolute maximum current injected per pin LU Pin current for latch up 200 200 mA Parameter Description Min Typ Max Units Details Conditions RFO RF output power on ANT 18 0 3 dBm Configurable via register settings RXS RF receive sensitivity on A...

Page 15: ... C Deep Sleep Mode VDD 1 71 V to 1 89 V Regulator Bypassed IDD19 WDT with WCO on µA T 25 C IDD20 WDT with WCO on µA T 40 C to 85 C Hibernate Mode VDD 1 8 V to 3 6 V IDD27 GPIO and reset active 150 nA T 25 C VDD 3 3 V IDD28 GPIO and reset active nA T 40 C to 85 C Hibernate Mode VDD 3 6 V to 5 5 V IDD29 GPIO and reset active nA T 25 C VDD 5 V IDD30 GPIO and reset active nA T 40 C to 85 C Stop Mode V...

Page 16: ... 0 V VIL Input voltage LOW threshold 0 3 VDD V CMOS input LVTTL input VDD 2 7 V 0 3 VDD V LVTTL input VDD 2 7 V 0 8 V VOH Output voltage HIGH level VDD 0 6 V IOH 4 mA at 3 3 V VDD Output voltage HIGH level VDD 0 5 V IOH 1 mA at 1 8 V VDD VOL Output voltage LOW level 0 6 V IOL 8 mA at 3 3 V VDD Output voltage LOW level 0 6 V IOL 4 mA at 1 8 V VDD Output voltage LOW level 0 4 V IOL 3 mA at 3 3 V VDD...

Page 17: ...iption Min Typ Max Units Details Conditions IIL Input leakage absolute value VIH VDD 10 µA 25 C VDD 0 V VIH 3 0 V VOL Output voltage LOW level 0 4 V IOL 20 mA VDD 2 9 V Table 14 OVT GPIO AC Specifications P5_0 and P5_1 Only Parameter Description Min Typ Max Units Details Conditions TRISE_OVFS Output rise time in Fast Strong mode 1 5 12 ns 25 pF load 10 90 VDD 3 3 V TFALL_OVFS Output fall time in F...

Page 18: ...S Number of channels single ended 8 8 full speed 8 A CHNKS_D Number of channels differential 4 Diff inputs use neighboring I O 8 A MONO Monotonicity Yes A_GAINERR Gain error 0 1 With external reference A_OFFSET Input offset voltage 2 mV Measured with 1 V VREF A_ISAR Current consumption 1 mA A_VINS Input voltage range single ended VSS VDDA V A_VIND Input voltage range differential VSS VDDA V A_INRE...

Page 19: ...eter Description Min Typ Max Units Details Conditions CSD Block Specifications Parameter Description Min Typ Max Units Details Conditions VCSD Voltage range of operation 1 71 5 5 V IDAC1 DNL for 8 bit resolution 1 1 LSB IDAC1 INL for 8 bit resolution 3 3 LSB IDAC2 DNL for 7 bit resolution 1 1 LSB IDAC2 INL for 7 bit resolution 3 3 LSB SNR Ratio of counts of finger to noise 5 Ratio Capacitance rang...

Page 20: ... ns TTENWIDEXT Enable pulse width external 2 TCLK ns TTIMRESWINT Reset pulse width internal 2 TCLK ns TTIMRESEXT Reset pulse width external 2 TCLK ns Table 22 Counter DC Specifications Parameter Description Min Typ Max Units Details Conditions ICTR1 Block current consumption at 3 MHz 42 µA 16 bit counter ICTR2 Block current consumption at 12 MHz 130 µA 16 bit counter ICTR3 Block current consumptio...

Page 21: ... TCLK ns TPWMKILLEXT Kill pulse width external 2 TCLK ns TPWMEINT Enable pulse width internal 2 TCLK ns TPWMENEXT Enable pulse width external 2 TCLK ns TPWMRESWINT Reset pulse width internal 2 TCLK ns TPWMRESWEXT Reset pulse width external 2 TCLK ns Table 26 LCD Direct Drive DC Specifications Parameter Description Min Typ Max Units Details Conditions ILCDLOW Operating current in low power mode 17 ...

Page 22: ... Table 32 Fixed SPI DC Specifications Parameter Description Min Typ Max Units Details Conditions ISPI1 Block current consumption at 1 Mbps 360 µA ISPI2 Block current consumption at 4 Mbps 560 µA ISPI3 Block current consumption at 8 Mbps 600 µA Table 33 Fixed SPI AC Specifications Parameter Description Min Typ Max Units Details Conditions FSPI SPI operating frequency master 6x over sampling 8 MHz T...

Page 23: ...AC Specifications Parameter Description Min Typ Max Units Details Conditions TROWWRITE 9 Row block write time erase and program 20 ms Row block 128 bytes TROWERASE 9 Row erase time 13 ms TROWPROGRAM 9 Row program time after erase 7 ms TBULKERASE 9 Bulk erase time 128 KB 35 ms TDEVPROG 9 Total device program time 25 seconds FEND Flash endurance 100 K cycles FRET Flash retention TA 55 C 100 K P E cy...

Page 24: ...cription Min Typ Max Units Details Conditions VHBRTRIP BOD trip voltage in Hibernate 1 1 V Table 42 Voltage Monitor DC Specifications Parameter Description Min Typ Max Units Details Conditions VLVI1 LVI_A D_SEL 3 0 0000b 1 71 1 75 1 79 V VLVI2 LVI_A D_SEL 3 0 0001b 1 76 1 80 1 85 V VLVI3 LVI_A D_SEL 3 0 0010b 1 85 1 90 1 95 V VLVI4 LVI_A D_SEL 3 0 0011b 1 95 2 00 2 05 V VLVI5 LVI_A D_SEL 3 0 0100b...

Page 25: ...ts Details Conditions IIMO1 IMO operating current at 48 MHz 1000 µA IIMO2 IMO operating current at 24 MHz 325 µA IIMO3 IMO operating current at 12 MHz 225 µA IIMO4 IMO operating current at 6 MHz 180 µA IIMO5 IMO operating current at 3 MHz 150 µA Table 46 IMO AC Specifications Parameter Description Min Typ Max Units Details Conditions FIMOTOL3 Frequency variation from 3 to 48 MHz 2 With API called ...

Page 26: ...hannel interference Wanted signal at 67 dBm and Interferer at FRX 3 MHz 39 dB RF PHY Specification RCV LE CA 03 C CI5 Adjacent channel interference Wanted Signal at 67 dBm and Interferer at Image frequency FIMAGE 20 dB RF PHY Specification RCV LE CA 03 C CI3 Adjacent channel interference Wanted signal at 67 dBm and Interferer at Image frequency FIMAGE 1 MHz 30 dB RF PHY Specification RCV LE CA 03 ...

Page 27: ...kHz RF PHY Specification TRM LE CA 06 C FTX DR Maximum drift rate 20 20 kHz 50 µs RF PHY Specification TRM LE CA 06 C IBSE1 In band spurious emission at 2 MHz offset 20 dBm RF PHY Specification TRM LE CA 03 C IBSE2 In band spurious emission at 3 MHz offset 30 dBm RF PHY Specification TRM LE CA 03 C TXSE1 Transmitter spurious emissions average 1 0 GHz 55 5 dBm FCC 15 247 TXSE2 Transmitter spurious ...

Page 28: ... second BLE connection interval 6 1 µA TXP 0 dBm 20 ppm master and slave clock accuracy For empty PDU exchange General RF Specifications FREQ RF operating frequency 2400 2482 MHz CHBW Channel spacing 2 MHz DR On air data rate 1000 kbps IDLE2TX BLE IDLE to BLE TX transition time 120 140 µs IDLE2RX BLE IDLE to BLE RX transition time 75 120 µs RSSI Specifications RSSI ACC RSSI accuracy 5 dB RSSI RES ...

Page 29: ...he Cypress BLE module Table 51 Environmental Conditions for CYBLE 01201X X0 ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference EMI A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD pr...

Page 30: ...circuit different from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for help LABELING REQUIREMENTS The Original Equipment Manufacturer OEM must ensure that FCC labelling requirements are met This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as...

Page 31: ... 1 this device may not cause interference and 2 this device must accept any interference including interference that may cause undesired operation of the device Le présent appareil est conforme aux CNR d Industrie Canada applicables aux appareils radio exempts de licence L exploitation est autorisée aux deux conditions suivantes 1 l appareil ne doit pas produire de brouillage et 2 l utilisateur de...

Page 32: ...dule with type certification number 203 JN0509 End products that integrate CYBLE 012011 00 do not need additional MIC Japan certification for the end product End product can display the certification label of the embedded module KC Korea CYBLE 012011 00 is certified for use in Korea with certificate number MSIP CRM Cyp 2011 ...

Page 33: ...ils the orientation of the CYBLE 01201X X0 in the tape as well as the direction for unreeling Figure 11 Component Orientation in Tape and Unreeling Direction Table 52 Solder Reflow Peak Temperature Module Part Number Package Maximum Peak Temperature Maximum Time at Peak Temperature No of Cycles CYBLE 01201X X0 31 pad SMT 260 C 30 seconds 2 Table 53 Package Moisture Sensitivity Level MSL IPC JEDEC ...

Page 34: ...el dimensions used for the CYBLE 01201X X0 Figure 12 Reel Dimensions The CYBLE 01201X X0 is designed to be used with pick and place equipment in an SMT manufacturing environment The center of mass for the CYBLE 01201X X0 is detailed in Figure 13 Figure 13 CYBLE 01201X X0 Center of Mass Seen from Top ...

Page 35: ...ional information and a complete list of Cypress Semiconductor BLE products contact your local Cypress sales representative To locate the nearest Cypress office visit our website Acronyms Table 54 Ordering Information Part Number CPU Speed MHz Flash Size KB CapSense SCB TCPWM 12 Bit SAR ADC I2 S LCD Package Packing Certified CYBLE 012011 00 48 128 Yes 2 4 1 Msps Yes Yes 31 SMT Tape and Reel Yes CY...

Page 36: ...t KC Korea Certification MIC Ministry of Internal Affairs and Communications Japan PCB printed circuit board RX receive QDID qualification design ID SMT surface mount technology a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs TCPWM timer counter pulse width modulator PWM TUV Germany Technischer Überwachungs Verein Technical Inspectio...

Page 37: ...tification number Updated KC Korea section on page 32 to specify final KC certification number Added Packaging section Added Table 52 and Table 53 on page 33 B 5148398 DSO 02 23 2016 Remove Preliminary from datasheet header and release as final Update More Information section to add KBA210638 Certification Test Reports to reference list Updated orientation of module drawings in Figure 1 Figure 2 F...

Page 38: ... and Recommended External Components Updated Figure 7 and Figure 8 to specify that these are Seen from Bottom Updated Digital and Analog Capabilities and Connections Updated Table 4 Updated TCPWM column to add TCPWM capability on Port 2 pins Added Footnote 3 E 5553544 DSO 12 14 2016 Updated Electrical Specification Updated SAR ADC Updated Table 18 to add Note 8 to specify under what conditions the...

Page 39: ... the responsibility of the user of this document to properly design program and test the functionality and safety of any application made of this information and any resulting product Cypress products are not designed intended or authorized for use as critical components in systems designed or intended for the operation of weapons weapons systems nuclear installations life support devices or syste...

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