Cypress CY8CPROTO-062S3-4343W, Manual

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CY8CPROTO-062S3-4343W PSoC 62S3 Wi-Fi BT Prototyping Kit Guide, Doc. # 002-28070 Rev. *A 16
2. Kit Operation
This chapter introduces you to various features of the PSoC 62S3 Wi-Fi BT Prototyping Board,
including the theory of operation and the onboard programming and debugging functionality,
KitProg3 USB-UART and USB-I2C bridges.
2.1 Theory of Operation
The PSoC 62S3 Wi-Fi BT Prototyping Board is built around PSoC 6 MCU. Figure 2-1 shows the
block diagram of the PSoC 6 MCU device used in the PSoC 62S3 Wi-Fi BT Prototyping Board. For
details of device features, see the
device datasheet .
Figure 2-1. PSoC 6 MCU Block Diagram
WCO
RTC
BREG
Backup
Backup Control
IO Subsystem
Peripheral Interconnect (MMIO,PPU)
IOS
S GPIO
PCLK
16x GPIO w. AMUX Bus, 2X GPIO OVT, 46x GPIO
CPU Subsystem
System Interconnect (Multi Layer AHB, IPC, MPU/SMPU)
CRYPTO
AES,SHA,CRC,
TRNG,RSA,ECC
Initiator/MMIO
High Speed I/O Matrix, Smart I/O, Boundary Scan
1x S
C
B
I2
C
,SPI
PSoC 62
CY8C62x5
Digital DFT
Test
Analog DFT
System Resources
Power
Reset
Sleep Control
PWRSYS-LP/ULP
REF
POR
Reset Control
TestMode Entry
XRES
LVD
BOD
DeepSleep
Hibernate
Active/Sleep
LowePowerActive/Sleep
Power Modes
Backup
OVP
Clock
Clock Control
IMO
WDT
1xPLL
ECO
ILO
FLL
SWJ/MTB/CTI
MUL, NVIC, MPU
Cortex M0+
100 MHz (1.1V)
25 MHz (0.9V)
2x Smart IO
eFU
S
E
10
24
b
it
Prog.
Analog
SAR
ADC
(12-bit)
x1
SARMUX
SWJ/ETM/ITM/CTI
Cortex M4
150 MHz (1.1V)
50 MHz (0.9V)
FPU, NVIC, MPU
SONOS
FLASH
512+32 KB
FLASH Controller
8 KB $ 8 KB $
SRAM0
256 KB
SRAM Controller
ROM
64 KB
ROM Controller
Ser
ial Mem
o
ry I/F
Q
SPI w
ith
O
T
F
En
c
ry
p
ti
o
n
/D
e
c
ry
p
ti
o
n
1x S
D
HC
S
D
/S
D
IO
/e
MMC
2x L
P
COM
P
L
o
w P
o
w
e
r Co
m
p
a
ra
to
r
CSD
C
apS
e
n
s
e
Buck
1x C
A
N FD
DMA
MMIO
USB
-FS
Hos
t +
Device
FS
/L
S
PH
Y
DM
A
2 c
h
a
nne
ls
DW
1
22
c
h
ann
el
s
LCD
12x
TCPW
M
T
IM
E
R
,CT
R,
Q
D
, P
W
M
6x S
C
B
I2
C
,SPI,U
AR
T
DW
0
22
c
h
ann
el
s