CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
353
Digital Blocks
17.2.1.9
Receiver Register Definitions
There are three 8-bit Data registers and one 8-bit Control/Status register.
explains the meaning of these registers
in the context of Receiver operation. The Control registers are described beginning with section
17.2.1.10
DSM Register Definitions
There are three 8-bit Data registers and two Control registers (a 5-bit and a 2-bit).
explains the meaning of these
registers in the context of DSM operation. The Control registers are described beginning with section
.
17.2.2
DxCxxCR0 Register
The DxCxxCR0 Registers are the digital blocks’ Control registers.
Bits 7 to 1:
The bits for this register are described by func-
tion in
.
Bit 0: Enable.
This bit is used to synchronously enable or
disable the programmed function.
For a complete description of bit functionality, refer to the
DxCxxCR0 (Timer Control:000) register on page 134
Table 17-19. Receiver Data Register Descriptions
Name
Function
Description
DR0
Shifter
Not readable or writeable.
During normal operation, DR0 implements a Shift register for shifting in serial data from the RXD input.
DR1
NA
Not used in this function.
DR2
RX Buffer
Read only register.
After eight bits of data are received, the contents of the shifter (DR0) is transferred into the RX Buffer register and the RX
Reg Full status is set. The RX Reg Full status bit in the Control register is cleared when this register is read.
Table 17-20. DSM Data Register Descriptions
Name
Function
Description
DR0
Difference
Not directly readable or writeable.
During normal operation, DR0 stores the current value of a synchronous subtracter.
When disabled, a write to the DR1 initial minuend register is also simultaneously loaded into DR0 from the data bus.
When disabled, a read of DR0 returns 00h to the data bus and transfers the contents of DR0 to DR2. This register should not
be read when the subtracter is enabled.
DR1
Initial phase
Write only register.
Data in this register sets the initial data of the subtracter.
DR1 may only be written to when the function is disabled.
When disabled, a write to this register also transfers the initial value directly into DR0.
DR2
Density Value
Read write register.
DR2 functions as a subtrahend register.
When enabled, DR0 = DR0 – DR2 is performed. The carry out is outputted to the auxiliary output.
When disabled, a read of DR0 will transfer the contents of DR0 into DR2.
DR2 may be written to when the function is enabled or disabled.
When enabled, if the block frequency is 24 MHz or below, this register may be written to at any time, If the block frequency is
48 MHz, the DSM function should be disabled first.
Add.
Name
Rows
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,xxh
3, 2
KILL[3:0] NPS
TC
Pulse
Width
Capture Int
Enable
RW : 00
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
refer to the
Summary of Contents for CY8C28 series
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