Cypress CY14B101LA Specification Sheet Download Page 22

Page: 22 / 25

PRELIMINARY

CY14B101LA, CY14B101NA

Document #: 001-42879 Rev. *B

Page 22 of 25

Figure 18. 48-Pin SSOP (51-85061)

Package Diagrams

(continued)

51-85061 *C

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Summary of Contents for CY14B101LA

Page 1: ...AM with a nonvolatile element in each memory cell The memory is organized as 128K bytes of 8 bits each or 64K words of 16 bits each The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides infinite read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfe...

Page 2: ...3 A4 A5 A6 A11 A7 A14 A15 A16 NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 TSOP II Top View not to scale A10 NC WE DQ7 HSB NC VSS VCC VCAP NC x8 6 7 VSS DQ6 DQ5 DQ4 VCC A13 DQ3 A12 DQ2 DQ1 DQ0 BLE A9 CE A1 A2 A3 A4 A5 A6 A7 A8 A11 A10 A14 BHE OE A15 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ...

Page 3: ...ting OE HIGH BHE Input Byte High Enable Active LOW Controls DQ15 DQ8 BLE Input Byte Low Enable Active LOW Controls DQ7 DQ0 VSS Ground Ground for the Device Must be connected to the ground of the system VCC Power Supply Power Supply Inputs to the Device 3 0V 20 10 HSB 8 Input Output Hardware STORE Busy HSB When LOW this output indicates that a Hardware STORE is in progress When pulled LOW external ...

Page 4: ...s Hardware STORE activated by HSB Software STORE activated by an address sequence AutoStore on device power down The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B101LA CY14B101NA During a normal operation the device draws current from VCC to charge a capacitor connected to the VCAP pin This stored charge is used by the chip to perform a si...

Page 5: ...olled reads or OE controlled reads After the sixth address in the sequence is entered the STORE cycle commences and the chip is disabled HSB is driven low It is important to use read cycles and not write cycles in the sequence although it is not necessary that OE be LOW for a valid sequence After the tSTORE cycle time is fulfilled the SRAM is activated again for the read and write operation Softwa...

Page 6: ...be issued to save the AutoStore state through subsequent power down cycles The part comes from the factory with AutoStore enabled Data Protection The CY14B101LA CY14B101NA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations The low voltage condition is detected when VCC is less than VSWITCH If the CY14B101LA CY14B101NA is in...

Page 7: ...strial 70 70 52 mA mA mA ICC2 Average VCC Current during STORE All Inputs Don t Care VCC Max Average current for duration tSTORE 10 mA ICC3 11 AverageVCC Currentat tRC 200 ns 3V 25 C typical All I P cycling at CMOS levels Values obtained without output loads IOUT 0 mA 35 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs Don t Care VCC Max Average current for duration tSTORE 5 mA ISB V...

Page 8: ...itance TA 25 C f 1 MHz VCC 0 to 3 0V 7 pF COUT Output Capacitance 7 pF Thermal Resistance Parameter 14 Description Test Conditions 48 FBGA 48 SSOP 44 TSOP II 32 SOIC Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 28 82 TBD 31 11 TBD C W ΘJC Thermal Resistance Junction to Case ...

Page 9: ...0 0 0 ns tHZBE 14 Byte Disable to Output Inactive 8 10 15 ns SRAM Write Cycle tWC tWC Write Cycle Time 20 25 45 ns tPWE tWP Write Pulse Width 15 20 30 ns tSCE tCW Chip Enable To End of Write 15 20 30 ns tSD tDW Data Setup to End of Write 8 10 15 ns tHD tDH Data Hold After End of Write 0 0 0 ns tAW tAW Address Setup to End of Write 15 20 30 ns tSA tAS Address Setup to Start of Write 0 0 0 ns tHA tW...

Page 10: ...9 Figure 8 SRAM Write Cycle 1 WE Controlled 3 18 19 21 Address Valid Address Data Output Output Data Valid Standby Active High Impedance CE OE BHE BLE ICC tHZCE tRC tACE tAA tLZCE tDOE tLZOE tDBE tLZBE tPU tPD tHZBE tHZOE Data Output Data Input Input Data Valid High Impedance Address Valid Address Previous Data tWC tSCE tHA tBW tAW tPWE tSA tSD tHD tHZWE tLZWE WE BHE BLE CE Feedback ...

Page 11: ... Figure 10 SRAM Write Cycle 3 BHE and BLE Controlled 3 18 19 21 Data Output Data Input Input Data Valid High Impedance Address Valid Address tWC tSD tHD BHE BLE WE CE tSA tSCE tHA tBW tPWE Data Output Data Input Input Data Valid High Impedance Address Valid Address tWC tSD tHD BHE BLE WE CE tSCE tSA tBW tHA tAW tPWE Feedback ...

Page 12: ...p RECALL 27 VSWITCH VHDIS VVCCRISE tSTORE tSTORE tHHHD tHHHD tDELAY tDELAY tLZHSB tLZHSB tHRECALL tHRECALL HSB OUT Autostore POWER UP RECALL Read Write Inhibited RWI POWER UP RECALL Read Write BROWN OUT Autostore POWER UP RECALL Read Write POWER DOWN Autostore Note23 Note23 Note26 Notes 22 tHRECALL starts from the time VCC rises above VSWITCH 23 If an SRAM write has not taken place since the last ...

Page 13: ...gure 12 CE and OE Controlled Software STORE RECALL Cycle 28 Figure 13 Autostore Enable Disable Cycle tRC tRC tSA tCW tCW tSA tHA tLZCE tHZCE tHA tHA tHA tDELAY tSTORE tRECALL tHHHD tLZHSB High Impedance Address 1 Address 6 Address CE OE HSB STORE only DQ DATA RWI tRC tRC tSA tCW tCW tSA tHA tLZCE tHZCE tHA tHA tHA tDELAY Address 1 Address 6 Address CE OE DQ DATA tSS Notes 27 The software sequence ...

Page 14: ... tSTORE tHHHD tLZHSB Write latch set Write latch not set HSB IN HSB OUT DQ Data Out RWI HSB IN HSB OUT RWI HSB pin is driven high to VCC only by Internal SRAM is disabled as long as HSB IN is driven low HSB driver is disabled tDHSB 100kOhm resistor Address 1 Address 6 Address 1 Address 6 Soft Sequence Command tSS tSS CE Address VCC tSA tCW Soft Sequence Command tCW Notes 29 This is the amount of t...

Page 15: ...for x16 Configuration CE WE OE BHE BLE Inputs Outputs 2 Mode Power H X X X X High Z Deselect Power down Standby L X X H H High Z Output Disabled Active L H L L L Data Out DQ0 DQ15 Read Active L H L H L Data Out DQ0 DQ7 DQ8 DQ15 in High Z Read Active L H L L H Data Out DQ8 DQ15 DQ0 DQ7 in High Z Read Active L H H L L High Z Output Disabled Active L H H H L High Z Output Disabled Active L H H L H Hi...

Page 16: ... 32 pin SOIC CY14B101NA ZS20XCT 51 85087 44 pin TSOP II CY14B101NA ZS20XC 51 85087 44 pin TSOP II CY14B101NA BA20XCT 51 85128 48 ball FBGA CY14B101NA BA20XC 51 85128 48 ball FBGA CY14B101LA ZS20XIT 51 85087 44 pin TSOP II Industrial CY14B101LA ZS20XI 51 85087 44 pin TSOP II CY14B101LA BA20XIT 51 85128 48 ball FBGA CY14B101LA BA20XI 51 85128 48 ball FBGA CY14B101LA SP20XIT 51 85061 48 pin SSOP CY14...

Page 17: ... II CY14B101NA BA25XCT 51 85128 48 ball FBGA CY14B101NA BA25XC 51 85128 48 ball FBGA CY14B101LA ZS25XIT 51 85087 44 pin TSOP II Industrial CY14B101LA ZS25XI 51 85087 44 pin TSOP II CY14B101LA BA25XIT 51 85128 48 ball FBGA CY14B101LA BA25XI 51 85128 48 ball FBGA CY14B101LA SP25XIT 51 85061 48 pin SSOP CY14B101LA SP25XI 51 85061 48 pin SSOP CY14B101LA SZ25XIT 51 85127 32 pin SOIC CY14B101LA SZ25XI 5...

Page 18: ... FBGA CY14B101LA ZS45XIT 51 85087 44 pin TSOP II Industrial CY14B101LA ZS45XI 51 85087 44 pin TSOP II CY14B101LA BA45XIT 51 85128 48 ball FBGA CY14B101LA BA45XI 51 85128 48 ball FBGA CY14B101LA SP45XIT 51 85061 48 pin SSOP CY14B101LA SP45XI 51 85061 48 pin SSOP CY14B101LA SZ45XIT 51 85127 32 pin SOIC CY14B101LA SZ45XI 51 85127 32 pin SOIC CY14B101NA ZS45XIT 51 85087 44 pin TSOP II CY14B101NA ZS45X...

Page 19: ...peed 20 20 ns 25 25 ns Data Bus L x8 N x16 Density 101 1 Mb Voltage B 3 0V Cypress CY 14 B 101L A ZS 20 X C T NVSRAM 14 AutoStore Software STORE Hardware STORE Temperature C Commercial 0 to 70 C I Industrial 40 to 85 C Pb Free Package BA 48 FBGA ZS TSOP II 45 45 ns SP 48 SSOP SZ 32 SOIC Die revision Blank No Rev A 1st Rev Feedback ...

Page 20: ...70 PLANE SEATING PIN 1 I D 44 1 18 517 0 729 0 800 BSC 0 5 0 400 0 016 0 300 0 012 EJECTOR PIN R G O K E A X S 11 735 0 462 10 058 0 396 10 262 0 404 1 194 0 047 0 991 0 039 0 150 0 0059 0 050 0 0020 0 0315 18 313 0 721 10 058 0 396 10 262 0 404 0 597 0 0235 0 406 0 0160 0 210 0 0083 0 120 0 0047 BASE PLANE 0 10 004 22 23 TOP VIEW BOTTOM VIEW 51 85087 A Feedback ...

Page 21: ...age Diagrams continued A 1 A1 CORNER 0 75 0 75 Ø0 30 0 05 48X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 21 0 05 1 20 MAX C SEATING PLANE 0 53 0 05 0 25 C 0 15 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 3 75 5 25 B C D E F G H 6 5 4 6 5 2 3 1 D H F G E C B A 6 00 0 10 10 00 0 10 A 10 00 0 10 6 00 0 10 B 1 875 2 625 0 36 51 85128 D Feedback ...

Page 22: ...PRELIMINARY CY14B101LA CY14B101NA Document 001 42879 Rev B Page 22 of 25 Figure 18 48 Pin SSOP 51 85061 Package Diagrams continued 51 85061 C Feedback ...

Page 23: ...PRELIMINARY CY14B101LA CY14B101NA Document 001 42879 Rev B Page 23 of 25 Figure 19 32 Pin SOIC 51 85127 Package Diagrams continued Feedback ...

Page 24: ...anged ICC4 from 6mA to 5mA Changed ISB from 3mA to 5mA Added IIX for HSB Updated ICC1 ICC3 ISB and IOZ Test conditions Changed VCAP voltage min value from 68uF to 61uF Added VCAP voltage max value to 180uF Updated footnote 12 and 13 Added footnote 14 Added Data retention and Endurance Table Added thermal resistance value to 48 pin FBGA and 44 pin TSOP II packages Updated Input Rise and Fall time i...

Page 25: ...re and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IM...

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