PRELIMINARY
CY14B101LA, CY14B101NA
Document #: 001-42879 Rev. *B
Page 4 of 25
Device Operation
The CY14B101LA/CY14B101NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B101LA/CY14B101NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations. Refer to the
Truth Table For SRAM Operations
on
page 15
for a complete description of read and write modes.
SRAM Read
The CY14B101LA/CY14B101NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A
0-16
or A
0-15
determines which of the 131,072
data bytes or 65,536 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of t
AA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t
ACE
or at t
DOE
, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
t
AA
access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ
0–15
are written into the memory if the data is valid t
SD
before the end
of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers t
HZWE
after WE goes LOW.
AutoStore Operation
The CY14B101LA/CY14B101NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
STORE activated by HSB; Software STORE activated by an
address sequence; AutoStore on device power down. The
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the
CY14B101LA/CY14B101NA.
During a normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Figure 4
shows the proper connection of the storage capacitor
(V
CAP
) for automatic STORE operation. Refer to
DC Electrical
Characteristics
on page 7 for the size of V
CAP
. The voltage on
the V
CAP
pin is driven to V
CC
by a regulator on the chip. Place a
pull up on WE to hold it inactive during power up. This pull up is
only effective if the WE signal is tri-state during power up. Many
MPUs tri-state their controls on power up. This must be verified
when using the pull up. When the nvSRAM comes out of
power-on-recall, the MPU must be active or the WE held inactive
until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
Hardware STORE Operation
The CY14B101LA/CY14B101NA provides the HSB
[8]
pin to
control and acknowledge the STORE operations. Use the HSB
pin to request a Hardware STORE cycle. When the HSB pin is
driven LOW, the CY14B101LA/CY14B101NA conditionally
initiates a STORE operation after t
DELAY
. An actual STORE cycle
only begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
SRAM read and write operations that are in progress when HSB
is driven LOW by any means are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14B101LA/CY14B101NA continues SRAM operations for
t
DELAY
. However, any SRAM write cycles requested after HSB
goes LOW are inhibited until HSB returns HIGH. If the write latch
is not set, HSB is not driven low by the
CY14B101LA/CY14B101NA, but any SRAM read/write cycles
are inhibited until HSB is returned HIGH by MPU or another
external source.
0.1uF
Vcc
10
kOhm
V
CAP
Vcc
WE
V
CAP
V
SS
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