Cypress Semiconductor SMD5962-92324 Specification Sheet Download Page 13 | Manualshive

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STK11C68-5 (SMD5962-92324)

Document Number: 001-51001 Rev. *A

Page 13 of 15

Package Diagrams

Figure 12. 28-Pin (300-Mil) Side Braze DIL (001-51695)

001-51695 **

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Summary of Contents for SMD5962-92324

Page 1: ...tile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology to produce the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers under software control from SRAM to the nonvolatile elements the STORE operation On power up d...

Page 2: ...ed and WE is LOW data on the I O pins is written to the specific address location CE E Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the I O pins to tristate VSS Ground Ground for the Device The device is connected to ...

Page 3: ...ad sequence is performed 1 Read address 0x0000 Valid READ 2 Read address 0x1555 Valid READ 3 Read address 0x0AAA Valid READ 4 Read address 0x1FFF Valid READ 5 Read address 0x10F0 Valid READ 6 Read address 0x0F0F Initiate STORE cycle The software sequence is clocked with CE controlled Reads When the sixth address in the sequence is entered the STORE cycle commences and the chip is disabled It is im...

Page 4: ...lity assurance Incoming inspection routines at customer or contract manufacturer s sites sometimes reprograms these values Final NV patterns are typically repeating patterns of AA 55 00 FF A5 or 5A The end product s firmware must not assume that an NV array is in a set programmed state Routines that check memory content values to determine first time system configuration Cold or warm boot status a...

Page 5: ...CC 0 2V All other inputs cycling Dependent on output loading and cycle rate Values obtained without output loads 10 mA ISB1 2 VCC Standby Current Standby Cycling TTL Input Levels tRC 35 ns CE VIH tRC 45 ns CE VIH tRC 55 ns CE VIH 24 21 20 mA mA mA ISB2 2 VCC Standby Current CE VCC 0 2V All others VIN 0 2V or VCC 0 2V Standby current level after nonvolatile cycle is complete Inputs are static f 0 M...

Page 6: ...A Thermal Resistance Junction to Ambient Test conditions follow standard test methods and proce dures for measuring thermal impedance per EIA JESD51 TBD TBD C W ΘJC Thermal Resistance Junction to Case TBD TBD C W Figure 5 AC Test Loads AC Test Conditions 5 0V Output 30 pF R1 480Ω R2 255Ω Input Pulse Levels 0V to 3V Input Rise and Fall Times 10 to 90 5 ns Input and Output Timing Reference Levels 1 ...

Page 7: ... Change 5 5 5 ns tLZCE 6 tELQX Chip Enable to Output Active 5 5 5 ns tHZCE 6 tEHQZ Chip Disable to Output Inactive 13 15 25 ns tLZOE 6 tGLQX Output Enable to Output Active 0 0 0 ns tHZOE 6 tGHQZ Output Disable to Output Inactive 13 15 25 ns tPU 3 tELICCH Chip Enable to Power Active 0 0 0 ns tPD 3 tEHICCL Chip Disable to Power Standby 35 45 55 ns Switching Waveforms Figure 6 SRAM Read Cycle 1 Addre...

Page 8: ...Address Setup to End of Write 25 30 45 ns tSA tAVWL tAVEL Address Setup to Start of Write 0 0 0 ns tHA tWHAX tEHAX Address Hold After End of Write 0 0 0 ns tHZWE 6 7 tWLQZ Write Enable to Output Disable 13 15 35 ns tLZWE 6 tWHQX Output Active After End of Write 5 5 5 ns Switching Waveforms Figure 8 SRAM Write Cycle 1 WE Controlled 7 8 Notes 7 If WE is Low when CE goes Low the outputs remain in the...

Page 9: ...w Voltage Trigger Level 4 0 4 5 V VRESET Low Voltage Reset Level 3 6 V Figure 10 AutoStore INHIBIT Power Up RECALL VCC VSWITCH VRESET POWER UP RECALL DQ DATA OUT STORE INHIBIT 5V tHRECALL POWER UP RECALL BROWN OUT STORE INHIBIT NO RECALL VCC DID NOT GO BELOW VRESET BROWN OUT STORE INHIBIT NO RECALL VCC DID NOT GO BELOW VRESET BROWN OUT STORE INHIBIT RECALL WHEN VCC RETURNS ABOVE VSWITCH Notes 9 tH...

Page 10: ... 25 30 35 ns tHACE 10 tELAX Address Hold Time 20 20 20 ns tRECALL 10 RECALL Duration 20 20 20 μs Switching Waveform Figure 11 CE Controlled Software STORE RECALL Cycle 10 Notes 10 The software sequence is clocked on the falling edge of CE without involving OE double clocking aborts the sequence 11 The six consecutive addresses must be read in the order listed in Table 1 on page 4 WE must be HIGH d...

Page 11: ... M Military 55 to 125 C K L Ceramic 28 pin LLC Ceramic 28 pin 300 mil DIP Solder dip finish Retention Endurance 5 Military 10 years or 105 cycles 55 55 ns Case Outline X Ceramic 28 pin 300 mil DIP Y Ceramic 28 pin LLC Device Class Indicator Class M SMD5962 92324 04 MX X Lead Finish A Solder DIP lead finish Device Type 04 55 ns 05 45 ns C Gold lead DIP finish X Lead finish A or C is acceptable 06 3...

Page 12: ...P 300 mil STK11C68 5L35M 001 51696 28 Pin LCC 350 mil 45 STK11C68 5C45M 001 51695 28 Pin CDIP 300 mil STK11C68 5K45M 001 51695 28 Pin CDIP 300 mil STK11C68 5L45M 001 51696 28 Pin LCC 350 mil 55 STK11C68 5C55M 001 51695 28 Pin CDIP 300 mil STK11C68 5K55M 001 51695 28 Pin CDIP 300 mil STK11C68 5L55M 001 51696 28 Pin LCC 350 mil This table contains Final information Contact your local Cypress sales r...

Page 13: ...STK11C68 5 SMD5962 92324 Document Number 001 51001 Rev A Page 13 of 15 Package Diagrams Figure 12 28 Pin 300 Mil Side Braze DIL 001 51695 001 51695 Feedback ...

Page 14: ...cument Number 001 51001 Rev A Page 14 of 15 Figure 13 28 Pad 350 Mil LCC 001 51696 Package Diagrams continued 1 ALL DIMENSION ARE IN INCHES AND MILLIMETERS MIN MAX 2 JEDEC 95 OUTLINE MO 041 3 PACKAGE WEIGHT TBD 001 51696 Feedback ...

Page 15: ...Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reser...

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