STK11C68-5 (SMD5962-92324)
Document Number: 001-51001 Rev. *A
Page 10 of 15
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
[10, 11]
Parameter
Alt
Description
35 ns
45 ns
55 ns
Unit
Min
Max
Min
Max
Min
Max
t
RC
t
AVAV
STORE/RECALL Initiation Cycle Time
35
45
55
ns
t
SA
[10]
t
AVEL
Address Setup Time
0
0
0
ns
t
CW
[10]
t
ELEH
Clock Pulse Width
25
30
35
ns
t
HACE
[10]
t
ELAX
Address Hold Time
20
20
20
ns
t
RECALL
[10]
RECALL Duration
20
20
20
μ
s
Switching Waveform
Figure 11. CE Controlled Software STORE/RECALL Cycle
[10]
Notes
10. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
11. The six consecutive addresses must be read in the order listed in
Table 1
on page 4. WE must be HIGH during all six consecutive cycles.
t
RC
t
RC
t
SA
t
SCE
t
HACE
t
STORE
/ t
RECALL
DATA VALID
DATA VALID
6
#
S
S
E
R
D
D
A
1
#
S
S
E
R
D
D
A
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
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