Cypress Semiconductor Perform CY7C1354C Manual Download

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CY7C1354C
CY7C1356C

Document #: 38-05538 Rev. *G

Page 21 of 28

NOP,STALL and DESELECT Cycles

[23, 24, 26]

Note:

26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

Switching Waveforms

(continued)

READ

Q(A3)

CLK

CEN

ADV/LD

ADDRESS

D(A4)

Data

In-Out (DQ)

Q(A5)

WRITE

D(A4)

STALL

WRITE

D(A1)

READ

Q(A2)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

CHZ

D(A1)

Q(A2)

Q(A3)

[+] Feedback

Summary of Contents for Perform CY7C1354C

Page 1: ...cle This feature dramatically improves the throughput of data in systems that require frequent Write Read transitions The CY7C1354C and CY7C1356C are pin compatible and functionally equivalent to ZBT devices All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock The clo...

Page 2: ...R 1 WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LOGIC A0 A1 D1 D0 Q1 Q0 A0 A1 C ADV LD ADV LD E INPUT REGISTER 1 S E N S E A M P S O U T P U T R E G I S T E R S E CLK CEN WRITE DRIVERS ZZ Sleep Control Logic Block Diagram CY7C1356C 512K x 18 Selection Guide 250 MHz 200 MHz 166 MHz Unit Maximum Access Time 2 8 3 2 3 5 ns Maximum Operating Current 250 220 180 mA Ma...

Page 3: ...00 Pin TQFP Pinout A A A A A 1 A 0 V SS V DD A A A A A A A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VDD VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BWb BWa CE 3 V DD V SS CLK WE CEN OE NC 18 A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2...

Page 4: ... NC 288M A A A1 A0 VSS VDD NC CY7C1354C 256K 36 DQPc DQb A NC 36M DQc DQb DQc DQc DQc DQb DQb DQa DQa DQa DQa DQPa DQd DQd DQd DQd BWd 119 Ball BGA Pinout BWb 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R T U NC 36M DQa VDDQ NC 576M NC 1G NC DQb DQb DQb DQb A A A A NC 18M VDDQ CE2 A NC VDDQ NC VDDQ VDDQ VDDQ NC NC NC 144M NC 72M A DQb DQb DQb DQb NC NC NC NC TMS VDD A A DQPb A A ADV LD A CE3 NC VDD ...

Page 5: ...DQb VDD NC VDD DQa VDD VDDQ DQa VDDQ VDD VDD VDDQ VDD VDDQ DQa VDDQ A A VSS A A A DQb DQb DQb ZZ DQa DQa DQPa DQa A VDDQ A 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 576M NC 1G NC NC DQPb NC DQb A CE1 CE3 BWb CEN A CE2 NC DQb DQb MODE NC DQb DQb NC NC NC NC 36M NC 72M VDDQ BWa CLK WE VSS VSS VSS VSS VDDQ VSS VDD VSS VSS VSS NC VSS VSS VSS VSS VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ A A VDD VSS VD...

Page 6: ...first clock when emerging from a deselected state and when the device has been deselected CEN Input Synchronous Clock Enable Input active LOW When asserted LOW the clock signal is recognized by the SRAM When deasserted HIGH the clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required DQS I O Synchronous Bidirectional Data ...

Page 7: ...e ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must be driven LOW in order to load a new address into the SRAM as described in the Single Read Access section above The sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an interleaved burst sequence Both ...

Page 8: ...Third Address Fourth Address A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table MODE GND First Address Second Address Third Address Fourth Address A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ VDD 0 2V 50...

Page 9: ...L H L H L Write Bytes c b L H L L H Write Bytes c b a L H L L L Write Byte d DQd and DQPd L L H H H Write Bytes d a L L H H L Write Bytes d b L L H L H Write Bytes d b a L L H L L Write Bytes d c L L L H H Write Bytes d c a L L L H L Write Bytes d c b L L L L H Write All Bytes L L L L L Partial Write Cycle Description 2 3 4 9 Function CY7C1356C WE BWb BWa Read H x x Write No Bytes Written L H H Wr...

Page 10: ...ernally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connect...

Page 11: ...e when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state EXTEST EXTEST is a mandatory 1149 1 instruction which is to be executed whenever the instruction register is loaded with ...

Page 12: ...r future use Do not use these instructions TAP Timing TAP AC Switching Characteristics Over the Operating Range 10 11 Parameter Description Min Max Unit Clock tTCYC TCK Clock Cycle Time 50 ns tTF TCK Clock Frequency 20 MHz tTH TCK Clock HIGH time 20 ns tTL TCK Clock LOW time 20 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns Set up Times tTMSS TMS Set...

Page 13: ...e IOH 4 0 mA VDDQ 3 3V 2 4 V IOH 1 0 mA VDDQ 2 5V 2 0 V VOH2 Output HIGH Voltage IOH 100 µA VDDQ 3 3V 2 9 V VDDQ 2 5V 2 1 V VOL1 Output LOW Voltage IOL 8 0 mA VDDQ 3 3V 0 4 V VDDQ 2 5V 0 4 V VOL2 Output LOW Voltage IOL 100 µA VDDQ 3 3V 0 2 V VDDQ 2 5V 0 2 V VIH Input HIGH Voltage VDDQ 3 3V 2 0 VDD 0 3 V VDDQ 2 5V 1 7 VDD 0 3 V VIL Input LOW Voltage VDDQ 3 3V 0 3 0 8 V VDDQ 2 5V 0 3 0 7 V IX Input ...

Page 14: ... and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the Input Output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the Input Output ring contents Places the boundary scan regist...

Page 15: ... M6 K11 25 L7 L11 26 K6 M11 27 P6 N11 28 T4 R11 29 A3 R10 30 C5 P10 31 B5 R9 32 A5 P9 33 C6 R8 34 A6 P8 35 P4 R6 36 N4 P6 37 R6 R4 38 T5 P4 39 T3 R3 40 R2 P3 41 R3 R1 42 P2 N1 43 P1 L2 44 L2 K2 45 K1 J2 46 N2 M2 47 N1 M1 48 M2 L1 49 L1 K1 50 K2 J1 51 Not Bonded Preset to 1 Not Bonded Preset to 1 52 H1 G2 53 G2 F2 54 E2 E2 55 D1 D2 56 H2 G1 57 G1 F1 58 F2 E1 59 E1 D1 60 D2 C1 61 C2 B2 62 A2 A2 63 E...

Page 16: ...P10 31 B5 R9 32 A5 P9 33 C6 R8 34 A6 P8 35 P4 R6 36 N4 P6 37 R6 R4 38 T5 P4 39 T3 R3 40 R2 P3 41 R3 R1 42 Not Bonded Preset to 0 Not Bonded Preset to 0 43 Not Bonded Preset to 0 Not Bonded Preset to 0 44 Not Bonded Preset to 0 Not Bonded Preset to 0 45 Not Bonded Preset to 0 Not Bonded Preset to 0 46 P2 N1 47 N1 M1 48 M2 L1 49 L1 K1 50 K2 J1 51 Not Bonded Preset to 1 Not Bonded Preset to 1 52 H1 G...

Page 17: ...3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA IDD VDD Operating Supply VDD Max IOUT 0 mA f fMAX 1 tCYC 4 ns cycle 250 MHz 250 mA 5 ns cycle 200 MHz 220 mA 6 ns cycle 166 MHz 1...

Page 18: ... Max Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 29 41 34 1 16 8 C W ΘJC Thermal Resistance Junction to Case 6 13 14 0 3 0 C W AC Test Loads and Waveforms OUTPUT R 317Ω R 351Ω 5 pF INCLUDING JIG AND SCOPE a b OUTPUT RL 50Ω Z0 50Ω VT 1 5V 3 3V ALL INPUT PULSES VDDQ GND 90 10 90 10 1 ns 1 n...

Page 19: ...before CLK Rise 1 4 1 5 1 5 ns tCES Chip Select Set up 1 4 1 5 1 5 ns Hold Times tAH Address Hold after CLK Rise 0 4 0 5 0 5 ns tDH Data Input Hold after CLK Rise 0 4 0 5 0 5 ns tCENH CEN Hold after CLK Rise 0 4 0 5 0 5 ns tWEH WE BWx Hold after CLK Rise 0 4 0 5 0 5 ns tALH ADV LD Hold after CLK Rise 0 4 0 5 0 5 ns tCEH Chip Select Hold after CLK Rise 0 4 0 5 0 5 ns Notes 17 This part has a voltag...

Page 20: ...t sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK t CYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BWX ADV LD tAH tAS ADDRESS A1 A2 A3 A4 A5 A6 A7 tDH tDS Data n Out DQ tCLZ D A1 D A2 D A5 Q A4 Q A3 D A2 1 tDOH tCHZ tCO WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q A6 WRIT...

Page 21: ...lustrated CEN being used to create a pause A write is not performed during this cycle Switching Waveforms continued READ Q A3 4 5 6 7 8 9 10 CLK CE WE CEN BWX ADV LD ADDRESS A3 A4 A5 D A4 Data In Out DQ A1 Q A5 WRITE D A4 STALL WRITE D A1 1 2 3 READ Q A2 STALL NOP READ Q A5 DESELECT CONTINUE DESELECT DON T CARE UNDEFINED tCHZ A2 D A1 Q A2 Q A3 Feedback ...

Page 22: ...ee cycle description table for all possible signal conditions to deselect the device 28 I Os are in High Z when exiting ZZ sleep mode ZZ Mode Timing 27 28 Switching Waveforms continued t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS except ZZ DON T CARE I DDZZ t ZZI tRZZI Outputs Q High Z DESELECT or READ Only Feedback ...

Page 23: ...id Array 14 x 22 x 2 4 mm Lead Free CY7C1356C 166BGXI CY7C1354C 166BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1356C 166BZI CY7C1354C 166BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1356C 166BZXI 200 CY7C1354C 200AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1356C 200AXC CY7C1354C 200BGC 51 85115 119...

Page 24: ... Lead Free CY7C1356C 250BZXC CY7C1354C 250AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1356C 250AXI CY7C1354C 250BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1356C 250BGI CY7C1354C 250BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1356C 250BGXI CY7C1354C 250BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm C...

Page 25: ...IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 08 MIN TYP 0 20 MAX 0 15 MAX 0 20 MAX R 0 08 MIN 0 20 MAX 14 00 0 10 16 00 0 20 0 10 SEE DETAIL A DETAIL A 1 100 30 31 50 51 80 81 GAUGE PLANE 1 00 REF 0 20 MIN SEATING PLANE 100 Pin Thin Plastic Quad...

Page 26: ... J U P N M T R 12 00 19 50 30 TYP 2 40 MAX A1 CORNER 0 70 REF U T R P N M L K J H G F E D C A B 2 1 4 3 6 5 7 Ø1 00 3X REF 7 62 22 00 0 20 14 00 0 20 1 27 0 60 0 10 C 0 15 C B A 0 15 4X Ø0 05 M C Ø0 75 0 15 119X Ø0 25 M C A B SEATING PLANE 0 90 0 05 3 81 10 16 0 25 C 0 56 51 85115 B 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 Feedback ...

Page 27: ...ctor Corporation ZBT is a trademark of Integrated Device Technology Inc All product and company names mentioned in this document are the trademarks of their respective holders A 1 PIN 1 CORNER 15 00 0 10 13 00 0 10 7 00 1 00 Ø0 50 165X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J...

Page 28: ...ide Changed ΘJA and ΘJC for TQFP Package from 25 and 9 C W to 29 41 and 6 13 C W respectively Changed ΘJA and ΘJC for BGA Package from 25 and 6 C W to 34 1 and 14 0 C W respectively Changed ΘJA and ΘJC for FBGA Package from 27 and 6 C W to 16 8 and 3 0 C W respectively Modified VOL VOH test conditions Added Lead Free product information Updated Ordering Information Table Changed from Preliminary t...

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