CY7C1354C
CY7C1356C
Document #: 38-05538 Rev. *G
Page 12 of 28
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
[10, 11]
Parameter
Description
Min.
Max.
Unit
Clock
t
TCYC
TCK Clock Cycle Time
50
ns
t
TF
TCK Clock Frequency
20
MHz
t
TH
TCK Clock HIGH time
20
ns
t
TL
TCK Clock LOW time
20
ns
Output Times
t
TDOV
TCK Clock LOW to TDO Valid
10
ns
t
TDOX
TCK Clock LOW to TDO Invalid
0
ns
Set-up Times
t
TMSS
TMS Set-up to TCK Clock Rise
5
ns
t
TDIS
TDI Set-up to TCK Clock Rise
5
ns
t
CS
Capture Set-up to TCK Rise
5
ns
Hold Times
t
TMSH
TMS Hold after TCK Clock Rise
5
ns
t
TDIH
TDI Hold after Clock Rise
5
ns
t
CH
Capture Hold after Clock Rise
5
ns
Notes:
10. t
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. t
R
/t
F
= 1 ns.
t
TL
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED
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