Cypress Semiconductor MoBL CY62157EV30 Specification Sheet Download Page 12 | Manualshive

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CY62157EV30 MoBL

®

Document #: 38-05445 Rev. *E

Page 12 of 14

Figure 10. 44-Pin TSOP II, 51-85087

Package Diagrams

(continued)

51-85087-*A

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Summary of Contents for MoBL CY62157EV30

Page 1: ...GH The input or output pins IO0 through IO15 are placed in a high impedance state when Deselected CE1HIGH or CE2 LOW Outputs are disabled OE HIGH Both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH Write operation is active CE1 LOW CE2 HIGH and WE LOW To write to the device take Chip Enable CE1 LOW and CE2 HIGH and Write Enable WE inputs LOW If Byte Low Enable BLE is LOW then data ...

Page 2: ...E A18 A17 A7 A6 A5 A4 A3 A2 A1 A16 BYTE Vss IO15 A19 IO7 IO14 IO6 IO13 IO5 IO12 IO4 Vcc IO11 IO3 IO10 IO2 IO9 IO1 IO8 IO0 OE Vss CE1 A0 A5 44 Pin TSOP II Top View A6 A7 A4 A3 A2 A1 A0 A17 A18 A9 A10 A11 A12 A15 A16 A14 A13 OE BHE BLE CE WE IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 VCC VCC VSS VSS A8 48 Pin TSOP I 512K x 16 1M x 8 Top View Notes 2 Typical values are incl...

Page 3: ...ll VFBGA pinout 3 4 5 Pin Configuration continued WE VCC A11 A10 NC A6 A0 A3 CE1 IO10 IO8 IO9 A4 A5 IO11 IO13 IO12 IO14 IO15 VSS A9 A8 OE VSS A7 IO0 BHE CE2 A2 A1 BLE VCC IO2 IO1 IO3 IO4 IO5 IO6 IO7 A15 A14 A13 A12 NC A18 NC 3 2 6 5 4 1 D E B A C F G H A16 A17 48 Ball VFBGA Top View Feedback ...

Page 4: ...IL Input LOW Voltage VCC 2 2V to 2 7V 0 3 0 6 V VCC 2 7V to 3 6V 0 3 0 8 V IIX Input Leakage Current GND VI VCC 1 1 µA IOZ Output Leakage Current GND VO VCC Output Disabled 1 1 µA ICC VCCOperatingSupplyCurrent f fmax 1 tRC VCC VCCmax IOUT 0 mA CMOS levels 18 25 mA f 1 MHz 1 8 3 ISB1 Automatic CE Power Down Current CMOS Inputs CE1 VCC 0 2V CE2 0 2V VIN VCC 0 2V VIN 0 2V f fmax Address and Data Only...

Page 5: ... Equivalent to THÉVENIN EQUIVALENT ALL INPUT PULSES RTH R1 TH Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ 2 Max Unit VDR VCC for Data Retention 1 5 V ICCDR 9 Data Retention Current VCC 1 5V CE1 VCC 0 2V CE2 0 2V VIN VCC 0 2V or VIN 0 2V Ind l Auto A 2 5 µA tCDR 10 Chip Deselect to Data Retention Time 0 ns tR 11 Operation Recovery Time tRC ns Dat...

Page 6: ...ta Hold from Write End 0 ns tHZWE WE LOW to High Z 15 16 18 ns tLZWE WE HIGH to Low Z 15 10 ns Notes 13 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns or less timing reference levels of VCC typ 2 input pulse levels of 0 to VCC typ and output loading of the specified IOL IOH as shown in the AC Test Loads and Waveforms on page 5 14 AC timing ...

Page 7: ... DATA VALID RC tAA tOHA tRC ADDRESS DATA OUT 50 50 DATA VALID tRC tACE tDOE tLZOE tLZCE tPU HIGH IMPEDANCE tHZOE tPD tHZBE tLZBE tHZCE tDBE OE CE1 ADDRESS CE2 BHE BLE DATA OUT VCC SUPPLY CURRENT HIGH ICC ISB IMPEDANCE Notes 19 The device is continuously selected OE CE1 VIL BHE BLE or both VIL and CE2 VIH 20 WE is HIGH for read cycle 21 Address valid before or similar to CE1 BHE BLE transition LOW ...

Page 8: ...tPWE tSA tHA tAW tSCE tWC tHZOE VALID DATA tBW NOTE 24 CE1 ADDRESS CE2 WE DATA IO OE BHE BLE tHD tSD tPWE tHA tAW tSCE tWC tHZOE VALID DATA tBW tSA NOTE 24 CE1 ADDRESS CE2 WE DATA IO OE BHE BLE Notes 22 Data IO is high impedance if OE VIH 23 If CE1 goes HIGH and CE2 goes LOW simultaneously with WE VIH the output remains in a high impedance state 24 During this period the IOs are in output state Do...

Page 9: ...le No 3 Write Cycle No 4 BHE BLE Controlled OE LOW 23 Figure 8 Write Cycle No 4 Switching Waveforms continued VALID DATA tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE tBW NOTE 24 CE1 ADDRESS CE2 WE DATA IO BHE BLE tHD tSD tSA tHA tAW tWC VALID DATA tBW tSCE tPWE NOTE 24 CE1 ADDRESS CE2 WE DATA IO BHE BLE Feedback ...

Page 10: ...ite Active ICC L H L X H L Data In IO0 IO7 High Z IO8 IO15 Write Active ICC L H L X L H High Z IO0 IO7 Data In IO8 IO15 Write Active ICC Ordering Information Speed ns Ordering Code Package Diagram Package Type Operating Range 45 CY62157EV30LL 45BVI 51 85150 48 ball Very Fine Pitch Ball Grid Array Industrial CY62157EV30LL 45BVXI 51 85150 48 ball Very Fine Pitch Ball Grid Array Pb free CY62157EV30LL...

Page 11: ...150 A 1 A1 CORNER 0 75 0 75 Ø0 30 0 05 48X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 21 0 05 1 00 MAX C SEATING PLANE 0 55 MAX 0 25 C 0 10 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 3 75 5 25 B C D E F G H 6 5 4 6 5 2 3 1 D H F G E C B A 6 00 0 10 8 00 0 10 A 8 00 0 10 6 00 0 10 B 1 875 2 625 0 26 MAX 51 85150 D Feedback ...

Page 12: ...CY62157EV30 MoBL Document 38 05445 Rev E Page 12 of 14 Figure 10 44 Pin TSOP II 51 85087 Package Diagrams continued 51 85087 A Feedback ...

Page 13: ... systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Figure 11 48 Pin TSOP I 12 mm x 18 4 mm x 1 0 mm 51 85183 MoBL is a registered trademark and More Batter...

Page 14: ... footnote on DNU Removed 35 ns speed bin Removed L bin Added 48 pin TSOP I package Added Automotive product information Changed the ICC Typ value from 16 mA to 18 mA and ICC Max value from 28 mA to 25 mA for test condition f fax 1 tRC Changed the ICC Max value from 2 3 mA to 3 mA for test condition f 1MHz Changed the ISB1 and ISB2 Max value from 4 5 µA to 8 µA and Typ value from 0 9 µA to 2 µA res...

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