Cypress Semiconductor MoBL CY62126EV30 Specification Sheet Download Page 8

Page: 8 / 13

MoBL

, CY62126EV30

Document #: 38-05486 Rev. *E

Page 8 of 13

Figure 9. Write Cycle No. 3

(WE controlled, OE LOW

[19]

Figure 10. Write Cycle No. 4

(BHE/BLE controlled, OE LOW)

[19]

Switching Waveforms

(continued)

DATA

LZWE

PWE

SCE

HZWE

NOTE 20

ADDRESS

DATA IO

BHE/BLE

DATA

SCE

PWE

HZWE

LZWE

NOTE 20

DATA IO

ADDRESS

BHE/BLE

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Summary of Contents for MoBL CY62126EV30

Page 1: ... addresses are not toggling Placing the device in standby mode reduces power consumption by more than 99 percent when deselected CE HIGH The input and output pins IO0 through IO15 are placed in a high impedance state when Deselected CE HIGH Outputs are disabled OE HIGH Both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH Write operation is active CE LOW and WE LOW To write to the de...

Page 2: ...he die 3 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at VCC VCC typ TA 25 C Product Range VCC Range V Speed ns Power Dissipation Operating ICC mA Standby ISB2 μA f 1 MHz f fmax Min Typ 3 Max Typ 3 Max Typ 3 Max Typ 3 Max CY62126EV30LL Industrial 2 2 3 0 3 6 45 1 3 2 11 16 1 4 CY62126EV30LL Automotive 2 2 3 0 3 6 55 1 3 4 11 35 1 30 Fe...

Page 3: ...C 2 7V to 3 6V 2 2 VCC 0 3 2 2 VCC 0 3 V VIL Input LOW Voltage VCC 2 2V to 2 7V 0 3 0 6 0 3 0 6 V VCC 2 7V to 3 6V 0 3 0 8 0 3 0 8 V IIX Input Leakage Current GND VI VCC 1 1 4 4 μA IOZ Output Leakage Current GND VO VCC Output Disabled 1 1 4 4 μA ICC VCC Operating Supply Current f fmax 1 tRC VCC VCCmax IOUT 0 mA CMOS levels 11 16 11 35 mA f 1 MHz 1 3 2 0 1 3 4 0 ISB1 Automatic CE Power down Current...

Page 4: ... Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ 1 Max Unit VDR VCC for Data Retention 1 5 V ICCDR 7 Data Retention Current VCC VDR CE VCC 0 2V VIN VCC 0 2V or VIN 0 2V Industrial 3 μA Automotive 30 μA tCDR 8 Chip Deselect to Data Retention Time 0 ns tR 9 Operation Recovery Time tRC ns Figure 4 Data Retention Waveform VCC VCC OUTPUT R2 30 pF INCLUDING JI...

Page 5: ...s tBW BHE BLE Pulse Width 35 40 ns tSD Data Setup to Write End 25 25 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High Z 12 13 18 20 ns tLZWE WE HIGH to Low Z 12 10 10 ns Notes 10 Test conditions assume signal transition time of 3 ns or less timing reference levels of VCC typ 2 input pulse levels of 0 to VCC typ and output loading of the specified IOL IOH and 30 pF load capacitance 11 AC...

Page 6: ... VALID DATA VALID tRC tAA tOHA ADDRESS DATA OUT 50 50 DATA VALID tRC tACE tLZBE tLZCE tPU HIGHIMPEDANCE ICC tHZOE tHZCE tPD tHZBE tLZOE tDBE tDOE IMPEDANCE HIGH ISB DATA OUT OE CE VCC SUPPLY CURRENT BHE BLE ADDRESS Notes 15 The device is continuously selected OE CE VIL BHE BLE or both VIL 16 WE is HIGH for read cycle 17 Address valid before or similar to CE and BHE BLE transition LOW Feedback ...

Page 7: ...E tSA tHA tAW tWC tHZOE DATAIN NOTE 20 tBW tSCE DATA IO ADDRESS CE WE OE BHE BLE tHD tSD tPWE tHA tAW tSCE tWC tHZOE DATAIN tBW tSA CE ADDRESS WE DATA IO OE BHE BLE NOTE 20 Notes 18 Data IO is high impedance if OE VIH 19 If CE goes HIGH simultaneously with WE VIH the output remains in a high impedance state 20 During this period the IOs are in output state Do not apply input signals Feedback ...

Page 8: ... OE LOW 19 Figure 10 Write Cycle No 4 BHE BLE controlled OE LOW 19 Switching Waveforms continued DATAIN tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE tBW NOTE 20 CE ADDRESS WE DATA IO BHE BLE tHD tSD tSA tHA tAW tWC DATAIN tBW tSCE tPWE tHZWE tLZWE NOTE 20 DATA IO ADDRESS CE WE BHE BLE Feedback ...

Page 9: ... Active ICC L L X L L Data In IO0 IO15 Write Active ICC L L X H L Data In IO0 IO7 IO8 IO15 in High Z Write Active ICC L L X L H Data In IO8 IO15 IO0 IO7 in High Z Write Active ICC Ordering Information Speed ns Ordering Code Package Diagram Package Type Operating Range 45 CY62126EV30LL 45BVXI 51 85150 48 ball Very Fine Pitch Ball Grid Array Pb free Industrial CY62126EV30LL 45ZSXI 51 85087 44 pin Th...

Page 10: ...5150 A 1 A1 CORNER 0 75 0 75 Ø0 30 0 05 48X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 21 0 05 1 00 MAX C SEATING PLANE 0 55 MAX 0 25 C 0 10 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 3 75 5 25 B C D E F G H 6 5 4 6 5 2 3 1 D H F G E C B A 6 00 0 10 8 00 0 10 A 8 00 0 10 6 00 0 10 B 1 875 2 625 0 26 MAX 51 85150 D Feedback ...

Page 11: ...MoBL CY62126EV30 Document 38 05486 Rev E Page 11 of 13 Figure 12 44 Pin TSOP II 51 85087 Package Diagrams continued 51 85087 A Feedback ...

Page 12: ...spectively Removed footnote that read BHE BLE is the AND of both BHE and BLE Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE on page 4 Removed footnote that read If both BHE and BLE are toggled together then tLZBE is 10 ns on page 5 Added Pb free package information B 461631 See ECN NXR Converted from Preliminary to Final Removed 35 ns Speed Bin ...

Page 13: ... or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED ...

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