Cypress Semiconductor CY7C64013C Specification Sheet Download Page 44 | Manualshive

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CY7C64013C

CY7C64113C

Document #: 38-08001 Rev. *B

Page 44 of 51

Note:

B: Read and Write
W: Write
R: Read

21.0

Sample Schematic

RE

SER

VE

D

0x48

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

00000000

0x49

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

00000000

0x4A

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

00000000

0x4B

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

00000000

0x4C

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

--000000

0x4D

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

00000000

0x4E

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

00000000

0x4F

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

00000000

0x50

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

00000000

0x51

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

00000000

0x52

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

00000000

0xFF

Process Status &

Control

IRQ

Pending

Watchdog

Reset

USB Bus

Reset

Interrupt

Power-On

Reset

Suspend

Interrupt

Enable

Sense

Reserved

Run

RBBBBRBB

00010001

Address Register Name Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/Write/

Both/-

Default/

Reset

XTALO

XTALI

D0–
D0+

V

CC

Vr

e

f

Vpp

GND
GND

IN

GND

OUT

USB-B

Vbus

D–
D+

GND

.01

µ

F

6.000 MHz

22x2(R

ext

)

0V

0V

0V

Vbus

Vref

0V

.01

µ

F

0V

2.2

µ

F

2.2

µ

F

SHELL

10M

4.7 nF

250VAC

Optional

3.3V Regulator

(R

UUP

)

Vref

1.5K

[+] Feedback

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Summary of Contents for CY7C64013C

Page 1: ...12 Mbps Function CY7C64013C CY7C64113C Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 408 943 2600 Document 38 08001 Rev B Revised March 3 2006 Full Speed USB 12 Mbps Fun...

Page 2: ...dress Modes 16 5 6 1 Data Immediate 16 5 6 2 Direct 16 5 6 3 Indexed 16 6 0 CLOCKING 17 7 0 RESET 17 7 1 Power On Reset POR 17 7 2 Watchdog Reset WDR 17 8 0 SUSPEND MODE 18 9 0 GENERAL PURPOSE I O GPI...

Page 3: ...ess 34 18 2 USB Device Endpoints 35 18 3 USB Control Endpoint Mode Register 35 18 4 USB Non Control Endpoint Mode Registers 36 18 5 USB Endpoint Counter Registers 36 18 6 Endpoint Mode Count Registers...

Page 4: ...Register 24 Figure 11 3 Timer Block Diagram 24 Figure 12 1 HAPI I2C Configuration Register 24 Figure 13 1 I2 C Data Register 25 Figure 13 2 I2C Status and Control Register 25 Figure 15 1 Processor St...

Page 5: ...figuration 25 Table 12 2 I2C Port Configuration 25 Table 13 1 I2C Status and Control Register Bit Definitions 26 Table 14 1 Port 2 Pin and HAPI Configuration Bit Definitions 27 Table 16 1 Interrupt Ve...

Page 6: ...ether to drive a common output Each GPIO port can be configured as inputs with internal pull ups or open drain outputs or traditional CMOS outputs A Digital to Analog Conversion DAC port with programm...

Page 7: ...ignals for distribution within the microcontroller Memory The CY7C64013C and CY7C64113C have 8 KB of PROM Power on Reset Watchdog and Free running Time These parts include power on reset logic a Watch...

Page 8: ...AM USB SIE USB Transceiver D 0 D 0 Upstream USB Port P3 2 0 DAC PORT DAC 0 DAC 2 High Current Outputs CY7C64113C only 256 byte 8 KB Clock 6 MHz 12 MHz 8 bit CPU I2 C compatible interface enabled by fi...

Page 9: ...4 NC P3 6 P2 0 P2 2 GND P2 4 P2 6 DAC 0 VPP P0 0 P0 2 P0 4 P0 6 DAC 2 CY7C64113C 48 pin SSOP CY7C64013C 1 2 3 4 5 6 7 9 11 12 13 14 XTALIN 10 8 15 17 16 19 18 21 20 23 22 25 24 26 28 27 VCC P1 1 P1 0...

Page 10: ...4 45 47 46 GPIO Port 1 capable of sinking 7 mA typical P2 I O P2 6 2 19 9 20 8 21 P2 6 2 20 10 21 9 23 P2 7 0 18 32 17 33 15 35 14 36 GPIO Port 2 capable of sinking 7 mA typical HAPI is also supported...

Page 11: ...Hz 23 Timer MSB 0x25 R Upper 4 Bits of Free running Timer 24 WDT Clear 0x26 W Watchdog Timer Clear 18 I2C Control Status 0x28 R W I2C Status and Control 25 I2C Data 0x29 R W I2C Data 25 DAC Data 0x30...

Page 12: ...xpr data 0D 4 PUSH A 2D 5 OR A expr direct 0E 6 PUSH X 2E 5 OR A X expr index 0F 7 SWAP A X 2F 5 AND A expr data 10 4 SWAP A DSP 30 5 AND A expr direct 11 6 MOV expr A direct 31 5 AND A X expr index 1...

Page 13: ...ed by executing an XPAGE instruction As a result the last instruction executed within a 256 byte page of sequential code should be an XPAGE instruction The assembler directive XPAGEON causes the assem...

Page 14: ...timer interrupt vector 0x0008 USB address A endpoint 0 interrupt vector 0x000A USB address A endpoint 1 interrupt vector 0x000C USB address A endpoint 2 interrupt vector 0x000E USB address A endpoint...

Page 15: ...nt the PSP by two The Return from Interrupt RETI instruction decrements the PSP then restores the second byte from memory addressed by the PSP The PSP is decremented again and the first byte is restor...

Page 16: ...is actually a constant encoded in the instruction As an example consider the instruction that loads A with the constant 0xD8 MOV A 0D8h This instruction requires two bytes of code where the first byt...

Page 17: ...T or RETI in the firmware reset handler causes unpredictable execution results 7 1 Power On Reset POR When VCC is first applied to the chip the Power On Reset POR signal is asserted and the CY7C64x13C...

Page 18: ...cessor Status and Control Register must be set to resume a part out of suspend The clock oscillator restarts immediately after exiting suspend mode The microcontroller returns to a fully functional st...

Page 19: ...DRESS 0x01 Port 2 Data ADDRESS 0x02 Figure 9 1 Block Diagram of a GPIO Pin Bit 7 6 5 4 3 2 1 0 Bit Name P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 Read Write R W R W R W R W R W R W R W R W Reset 1 1 1 1...

Page 20: ...y on an input pin represents a rising edge interrupt LOW to HIGH and a negative polarity on an input pin represents a falling edge interrupt HIGH to LOW The GPIO interrupt is generated when all of the...

Page 21: ...rrupts are disabled by clearing all of the GPIO interrupt enable ports Writing a 1 to a GPIO Interrupt Enable bit enables GPIO interrupts from the corresponding input pin All GPIO pins share a common...

Page 22: ...output pulled HGH through the 14 k resistor 0 I O pin is an input with an internal 14 k pull up resistor Bit 3 2 Low Current Output 0 2 mA to 1 mA typical 1 I O pin is an output pulled HGH through the...

Page 23: ...corresponding input pin All of the DAC Port Interrupt Polarity register bits are cleared during a reset DAC Port Interrupt Polarity ADDRESS 0x32 Bit 7 0 Enable bit x x 0 2 7 1 Selects positive polarit...

Page 24: ...API port configurations and Table 12 2 shows I2C pin location configuration options These I2C compatible options exist due to pin limitations in certain packages and to allow simultaneous HAPI and I2...

Page 25: ...nctionality of the HAPI I2C Configuration Register which is used to set the locations of the configurable I2C compatible pins Once the I2C compatible functionality is enabled by setting bit 0 of the I...

Page 26: ...C address packet The Xmit Mode bit state is ignored when initially writing the MSTR Mode or the Restart bits as these cases always cause transmit mode for the first byte Bit 4 ACK This bit is set or...

Page 27: ...es the HAPI data to be output on the port pins When OE is returned HIGH inactive the HAPI GPIO interrupt is generated At that point firmware can reload the HAPI latches for the next output again writi...

Page 28: ...explained below Bit 5 USB Bus Reset Interrupt The USB Bus Reset Interrupt bit is set when the USB Bus Reset is detected on receiving a USB Bus Reset signal on the upstream port The USB Bus Reset sign...

Page 29: ...able ADDRESS 0X21 Bit 0 EPA0 Interrupt Enable 1 Enable Interrupt on data activity through endpoint A0 0 Disable Interrupt on data activity through endpoint A0 Bit 1 EPA1 Interrupt Enable 1 Enable Inte...

Page 30: ...mand in the ISR to save the accumulator value and the POP A instruction should be used to restore the accumulator value just before the RETI instruction The program counter CF and ZF are restored and...

Page 31: ...n servicing the timer interrupts first or the suspend request first 16 5 USB Endpoint Interrupts There are five USB endpoint interrupts one per endpoint A USB endpoint interrupt is generated after the...

Page 32: ...is generally involves reading the I2 C Status and Control Register Figure 13 2 to determine the cause of the interrupt loading reading the I2C Data Register as appropriate and finally writing the Stat...

Page 33: ...activity independently of the micro controller Bit stuffing unstuffing Checksum generation checking ACK NAK STALL Token type identification Address checking Firmware is required to handle the followi...

Page 34: ...EPA0 EPA1 EPA2 EPA3 and EPA4 Endpoint EPA0 allows the USB host to recognize set up and control the device In particular EPA0 is used to receive and transmit control including set up packets 18 1 USB...

Page 35: ...itialize and control each USB address Endpoint 0 provides access to the device configuration information and allows generic USB status and control accesses Endpoint 0 is bidirectional to both receive...

Page 36: ...riting an incoming SETUP transaction before firmware has a chance to read the SETUP data Refer to Table 18 1 for the appropriate endpoint zero memory locations The Mode bits bits 3 0 control how the e...

Page 37: ...ers of other endpoints 18 6 Endpoint Mode Count Registers Update and Locking Mechanism The contents of the endpoint mode and counter registers are updated based on the packet flow diagram in Figure 18...

Page 38: ...C Data Packet Device To Host NAK STALL UPDATE 2 OUT or SETUP Token without CRC error S Y N C O U T Set up A D D R C R C 5 E N D P Token Packet Host To Device S Y N C D A T A 1 0 C R C 16 Data Data Pac...

Page 39: ...in response to the IN token received A TX0 Byte entry in the IN column implies that the SIE transmit a zero length byte packet in response to the IN token received from the host An Ignore in any of t...

Page 40: ...The response of the SIE can be summarized as follows 1 The SIE will only respond to valid transactions and will ignore non valid ones 2 The SIE will generate an interrupt when a valid transaction is c...

Page 41: ...0 0 1 1 In x UC x UC UC UC UC 1 UC UC NoChange Stall yes CONTROL WRITE Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits Mode Bits token count buffer dval DTOG DVA...

Page 42: ...3 0 1 0 0 1 In x UC x UC UC UC UC UC UC UC NoChange Stall no STALL 3 1 NAK Out erroneous In 1 0 0 0 Out 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes 1 0 0 0 Out 10 UC x UC UC UC UC UC UC UC NoChan...

Page 43: ...t 3 Mode Bit 2 Mode Bit 1 Mode Bit 0 BBBBBBBB 00000000 0x15 EP A2 Counter Register Data 0 1 Toggle Data Valid Byte Count Bit 5 Byte Count Bit 4 Byte Count Bit 3 Byte Count Bit 2 Byte Count Bit 1 Byte...

Page 44: ...erved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 00000000 0x4F Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 00000000 0x50 Rese...

Page 45: ...A USB Interface Vdi Differential Input Sensitivity D D 0 2 V Vcm Differential Input Common Mode Range 0 8 2 5 V Vse Single Ended Receiver Threshold 0 8 2 0 V Cin Transceiver Capacitance 20 pF Ilo Hi Z...

Page 46: ...mfs Rise Fall Time Matching tr tf 90 111 tdratefs Full Speed Date Rate 12 0 25 Mb s DAC Interface tsink Current Sink Response Time 0 8 s HAPI Read Cycle Timing tRD Read Pulse Width 15 ns tOED OE LOW t...

Page 47: ...ng Figure 24 3 HAPI Read by External Interface from USB Microcontroller CLOCK tCYC tCL tCH 90 10 90 10 D D tr tr OE P2 5 input DATA output STB P2 4 input DReadyPin P2 3 output Internal Write Internal...

Page 48: ...n 300 Mil PDIP Commercial CY7C64013C SXCT 8 KB 28 Pin 300 Mil SOIC Tape Reel Commercial CY7C64113C PVXC 8 KB 48 Pin 300 Mil SSOP Commercial DATA input LEmptyPin P2 2 output Internal Read Internal Addr...

Page 49: ...0 055 1 39 0 065 1 65 0 015 0 38 0 020 0 50 0 015 0 38 0 060 1 52 0 120 3 05 0 140 3 55 0 009 0 23 0 012 0 30 0 310 7 87 0 385 9 78 0 290 7 36 0 325 8 25 0 030 0 76 0 080 2 03 0 115 2 92 0 160 4 06 0...

Page 50: ...user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges All produc...

Page 51: ...rom Spec number 38 00626 to 38 08001 A 129715 02 05 04 MON Added register bit definitions Added default bit state of each register Corrected the Schematic location of the Pull up on D Added register s...

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