CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B
Page 31 of 51
16.2
Interrupt Latency
Interrupt latency can be calculated from the following equation:
Interrupt latency =
(Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) +
(5 clock cycles for the JMP instruction)
For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine executes a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is
issued. For a 12-MHz internal clock (6-MHz crystal), 20 clock periods is 20 / 12 MHz = 1.667 µs.
16.3
USB Bus Reset Interrupt
The USB Controller recognizes a USB Reset when a Single Ended Zero (SE0) condition persists on the upstream USB port for
12–16 µs (the Reset may be recognized for an SE0 as short as 12 µs, but is always recognized for an SE0 longer than 16 µs).
SE0 is defined as the condition in which both the D+ line and the D– line are LOW. Bit 5 of the Status and Control Register is set
to record this event. The interrupt is asserted at the end of the Bus Reset. If the USB reset occurs during the start-up delay
following a POR, the delay is aborted as described in Section 7.1. The USB Bus Reset Interrupt is generated when the SE0 state
is deasserted.
A USB Bus Reset clears the following registers:
SIE Section:USB Device Address Registers (0x10, 0x40)
16.4
Timer Interrupt
There are two periodic timer interrupts: the 128- µs interrupt and the 1.024-ms interrupt. The user should disable both timer
interrupts before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts first or the suspend
request first.
16.5
USB Endpoint Interrupts
There are five USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to a
USB endpoint FIFO or after the USB controller sends a packet to the USB host. The interrupt is generated on the last packet of
the transaction (e.g., on the host’s ACK during an IN, or on the device ACK during on OUT). If no ACK is received during an IN
transaction, no interrupt is generated.
16.6
DAC Interrupt
Each DAC I/O pin can generate an interrupt, if enabled. The interrupt polarity for each DAC I/O pin is programmable. A positive
polarity is a rising edge input while a negative polarity is a falling edge input. All of the DAC pins share a single interrupt vector,
which means the firmware needs to read the DAC port to determine which pin or pins caused an interrupt.
If one DAC pin has triggered an interrupt, no other DAC pins can cause a DAC interrupt until that pin has returned to its inactive
(non-trigger) state or the corresponding interrupt enable bit is cleared. The USB Controller does not assign interrupt priority to
different DAC pins and the DAC Interrupt Enable Register is not cleared during the interrupt acknowledge process.
Table 16-1. Interrupt Vector Assignments
Interrupt Vector Number
ROM Address
Function
Not Applicable
0x0000
Execution after Reset begins here
1
0x0002
USB Bus Reset interrupt
2
0x0004
128- µs timer interrupt
3
0x0006
1.024-ms timer interrupt
4
0x0008
USB Address A Endpoint 0 interrupt
5
0x000A
USB Address A Endpoint 1 interrupt
6
0x000C
USB Address A Endpoint 2 interrupt
7
0x000E
USB Address A Endpoint 3 interrupt
8
0x0010
USB Address A Endpoint 4 interrupt
9
0x0012
Reserved
10
0x0014
DAC interrupt
11
0x0016
GPIO interrupt
12
0x0018
I
2
C interrupt
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