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Cypress Semiconductor CY7C1516KV18, Specification Sheet

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Cypress Semiconductor CY7C1516KV18 Specification Sheet Download Page 27

CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18

Document Number: 001-00437 Rev. *E

Page 27 of 30

250

CY7C1516KV18-250BZC

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) 

Commercial

CY7C1527KV18-250BZC
CY7C1518KV18-250BZC
CY7C1520KV18-250BZC
CY7C1516KV18-250BZXC

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-250BZXC
CY7C1518KV18-250BZXC
CY7C1520KV18-250BZXC
CY7C1516KV18-250BZI

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) 

Industrial

CY7C1527KV18-250BZI
CY7C1518KV18-250BZI
CY7C1520KV18-250BZI
CY7C1516KV18-250BZXI

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-250BZXI
CY7C1518KV18-250BZXI
CY7C1520KV18-250BZXI

200

CY7C1516KV18-200BZC

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) 

Commercial

CY7C1527KV18-200BZC
CY7C1518KV18-200BZC
CY7C1520KV18-200BZC
CY7C1516KV18-200BZXC

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-200BZXC
CY7C1518KV18-200BZXC
CY7C1520KV18-200BZXC
CY7C1516KV18-200BZI

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) 

Industrial

CY7C1527KV18-200BZI
CY7C1518KV18-200BZI
CY7C1520KV18-200BZI
CY7C1516KV18-200BZXI

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-200BZXI
CY7C1518KV18-200BZXI
CY7C1520KV18-200BZXI

Table 2.  Ordering Information 

 (continued)

Speed

(MHz)

Ordering Code

Package

Diagram

Package Type

Operating

Range

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Summary of Contents for CY7C1516KV18

Page 1: ...a 1 bit burst counter Addresses for read and write are latched on alternate rising edges of the input K clock Write data is registered on the rising edges of both K and K Read data is driven on the r...

Page 2: ...egister Read Add Decode Read Data Reg R W Output Logic Reg Reg Reg 8 16 8 NWS 1 0 VREF Write Add Decode 8 22 C C 8 LD Control R W DOFF 4M x 8 Array 4M x 8 Array 8 DQ 7 0 8 CQ CQ Write Reg Write Reg CL...

Page 3: ...eg R W Output Logic Reg Reg Reg 18 36 18 BWS 1 0 VREF Write Add Decode 18 22 C C 18 LD Control Burst Logic A0 A 21 1 R W DOFF 2M x 18 Array 2M x 18 Array 21 18 DQ 17 0 18 CQ CQ Write Reg Write Reg CLK...

Page 4: ...NC VDDQ VSS VSS VSS VDDQ NC NC DQ0 M NC NC NC VSS VSS VSS VSS VSS NC NC NC N NC NC NC VSS A A A VSS NC NC NC P NC NC DQ7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1527KV18 8M x 9 1 2 3 4...

Page 5: ...A A NC NC DQ0 R TDO TCK A A A C A A A TMS TDI CY7C1520KV18 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 144M A R W BWS2 K BWS1 LD A A CQ B NC DQ27 DQ18 A BWS3 K BWS0 A NC NC DQ8 C NC NC DQ28 VSS A A0 A VS...

Page 6: ...onous Address Inputs These address inputs are multiplexed for both read and write operations Internally the device is organized as 8M x 8 2 arrays each of 4M x 8 for CY7C1516KV18 and 8M x 9 2 arrays e...

Page 7: ...cannot be connected directly to GND or left unconnected DOFF Input PLL Turn Off Active LOW Connecting this pin to ground turns off the PLL inside the device The timing in the PLL turned off operation...

Page 8: ...ounter increments the address in a linear fashion On the following K clock rise the data presented to D 17 0 is latched and stored into the 18 bit write data register provided BWS 1 0 are both asserte...

Page 9: ...th respect to K and CQ is generated with respect to K The timing for the echo clocks is shown in the Switching Characteristics on page 23 PLL These chips use a PLL that is designed to function between...

Page 10: ...er byte D 8 0 is written into the device D 17 9 remains unaltered H L L H During the data portion of a write sequence CY7C1516KV18 only the upper nibble D 7 4 is written into the device D 3 0 remains...

Page 11: ...into the device D 35 9 remains unaltered L H H H L H During the data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the da...

Page 12: ...e falling edge of TCK Instruction Register Three bit instructions are serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in T...

Page 13: ...egister After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an...

Page 14: ...ontroller follows 9 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR S...

Page 15: ...t HIGH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 I...

Page 16: ...tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions...

Page 17: ...Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and T...

Page 18: ...L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P...

Page 19: ...and clock K K for 20 s to lock the PLL PLL Constraints PLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The PLL functions at frequencies d...

Page 20: ...V VOH Output HIGH Voltage Note 16 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 17 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Ou...

Page 21: ...tic 333 MHz x8 290 mA x9 290 x18 290 x36 290 300 MHz x8 280 mA x9 280 x18 280 x36 280 250 MHz x8 270 mA x9 270 x18 270 x36 270 200 MHz x8 250 mA x9 250 x18 250 x36 250 167 MHz x8 250 mA x9 250 x18 250...

Page 22: ...ient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 13 7 C W JC Thermal Resistance Junction to Case 3 73 C W Figure 4 AC Test...

Page 23: ...to K Clock Rise 0 4 0 4 0 5 0 6 0 7 ns tSC tIVKH Control Setup to K Clock Rise LD R W 0 4 0 4 0 5 0 6 0 7 ns tSCDDR tIVKH Double Data Rate Control Setup to Clock K K Rise BWS0 BWS1 BWS2 BWS3 0 3 0 3...

Page 24: ...Z Clock C C Rise to High Z Active to High Z 24 25 0 45 0 45 0 45 0 45 0 50 ns tCLZ tCHQX1 Clock C C Rise to Low Z 24 25 0 45 0 45 0 45 0 45 0 50 ns PLL Timing tKC Var tKC Var Clock Phase Jitter 0 20 0...

Page 25: ...KHKH tKL tCYC A0 D20 D21 D30 D31 Q00 Q11 Q01 Q10 A1 A2 A3 A4 Q41 tCCQO tCQOH tCCQO tCQOH tKL tCYC K K LD R W A DQ C C CQ CQ SA tKH tKHKH tCQD tCQDOH tCQH tCQHCQH Notes 26 Q00 refers to output from add...

Page 26: ...13 x 15 x 1 4 mm Commercial CY7C1527KV18 333BZC CY7C1518KV18 333BZC CY7C1520KV18 333BZC CY7C1516KV18 333BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1527KV18 333BZXC...

Page 27: ...ay 13 x 15 x 1 4 mm Pb Free CY7C1527KV18 250BZXI CY7C1518KV18 250BZXI CY7C1520KV18 250BZXI 200 CY7C1516KV18 200BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1527KV18...

Page 28: ...rray 13 x 15 x 1 4 mm Pb Free CY7C1527KV18 167BZXC CY7C1518KV18 167BZXC CY7C1520KV18 167BZXC CY7C1516KV18 167BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1527KV18 1...

Page 29: ...A B 0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M...

Page 30: ...RCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out...

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