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CY7C1511V18, CY7C1526V18

CY7C1513V18, CY7C1515V18

Document Number: 38-05363 Rev. *F

Page 31 of 32

Document History Page

Document Title: CY7C1511V18/CY7C1526V18/CY7C1513V18/CY7C1515V18, 72-Mbit QDR™-II SRAM 4-Word Burst Archi-
tecture
Document Number: 38-05363

REV.

ECN NO.

SUBMISSION

DATE

ORIG. OF 
CHANGE

DESCRIPTION OF CHANGE

**

226981

See ECN

DIM

New Data Sheet

*A

257089

See ECN

NJY

Modified JTAG ID code for x9 option in the ID register definition on page 20 of 
the data sheet
Included thermal values
Modified capacitance values table: included capacitance values for x8, x18 
and x36 options

*B

319496

See ECN

SYT

Removed CY7C1526V18 from the title
Included 300-MHz Speed Bin
Added footnote #1 and accordingly edited the V

SS

/144M And V

SS

/288M on 

the Pin Definitions table
Added Industrial temperature grade 
Replaced TBDs for I

DD

 and I

SB1

 for 300 MHz, 250 MHz, 200 MHz and 167 

MHz speed grades
Changed the C

IN

 from 5 pF to 5.5 pF and C

O

 from 7 pF to 8 pF in the 

Capacitance Table
Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS 
TRI-STATE on Page 17
Removed the capacitance value column for the x9 option from Capacitance 
Table
Added lead-free product information
Updated the Ordering Information by Shading and unshading as per avail-
ability

*C

403231

See ECN

NXR

Converted from Preliminary to Final
Added CY7C1526V18 part number to the title
Added 278-MHz speed Bin
Changed address of Cypress Semiconductor Corporation on Page# 1 from 
“3901 North First Street” to “198 Champion Court”
Changed C/C Pin Description in the features section and Pin Description 
Added power-up sequence details and waveforms
Added foot notes #16, 17, 18 on page# 19
Changed the description of I

X

 from Input Load Current to Input Leakage 

Current
on page# 20
Modified the I

DD

 and I

SB

 values

Modified test condition in Footnote #19 on page # 20 from V

DDQ 

< V

DD 

to 

V

DDQ 

< V

DD

Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table

*D

467290

See ECN

NXR

Modified the ZQ Definition from Alternately, this pin can be connected directly 
to V

DD 

to Alternately, this pin can be connected directly to V

DDQ

Included Maximum Ratings for Supply Voltage on V

DDQ

 Relative to GND

Changed the Maximum Ratings for DC Input Voltage from V

DDQ

 to V

DD

Changed t

TCYC 

from 100 ns to 50 ns, changed t

TH 

and t

TL 

from 40 ns to 20 ns, 

changed t

TMSS

, t

TDIS

, t

CS

, t

TMSH

, t

TDIH

, t

CH 

from

 

10 ns to 5 ns and changed 

t

TDOV 

from 20 ns to 10 ns in TAP AC Switching Characteristics table 

Modified Power-Up waveform
Changed the Maximum rating of Ambient Temperature with Power Applied 
from –10°C to +85°C to –55°C to +125°C
Added additional notes in the AC parameter section
Modified AC Switching Waveform
Updated the Typo in the AC Switching Characteristics Table
Updated the Ordering Information Table

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Summary of Contents for CY7C1511V18

Page 1: ...rts the read port and the write port to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operat...

Page 2: ...eg Reg Reg 16 21 32 8 NWS 1 0 VREF Write Add Decode Write Reg 16 A 20 0 21 8 CQ CQ DOFF Q 7 0 8 8 8 Write Reg Write Reg Write Reg C C 2M x 8 Array 2M x 8 Array 2M x 8 Array 8 CLK A 20 0 Gen K K Contro...

Page 3: ...VREF Write Add Decode Write Reg 36 A 19 0 20 18 CQ CQ DOFF Q 17 0 18 18 18 Write Reg Write Reg Write Reg C C 1M x 18 Array 1M x 18 Array 1M x 18 Array 1M x 18 Array 18 512K x 36 Array CLK A 18 0 Gen...

Page 4: ...VDDQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1526V18 8M x 9 1 2 3 4 5 6 7...

Page 5: ...A NC D0 Q0 R TDO TCK A A A C A A A TMS TDI CY7C1515V18 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS 288M A WPS BWS2 K BWS1 RPS A VSS 144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A N...

Page 6: ...7C1511V18 8M x 9 4 arrays each of 2M x 9 for CY7C1526V18 4M x 18 4 arrays each of 1M x 18 for CY7C1513V18 and 2M x 36 4 arrays each of 512K x 36 for CY7C1515V18 Therefore only 21 address inputs are ne...

Page 7: ...connected between ZQ and ground Alternatively this pin can be connected directly to VDDQ which enables the minimum impedance mode This pin cannot be connected directly to GND or left unconnected DOFF...

Page 8: ...l logic of the device ignores the second read request Read accesses can be initiated on every other K clock rise Doing so pipelines the data flow such that data is transferred out of the device on eve...

Page 9: ...input can deselect the specified port Deselecting a port does not affect the other port All pending transactions read and write are completed before the device is deselected Programmable Impedance An...

Page 10: ...S ZQ CQ CQ Q K BUS MASTER CPU or ASIC DATA IN DATA OUT Address RPS WPS BWS Source K Source K Delayed K Delayed K CLKIN CLKIN Notes 2 X Don t Care H Logic HIGH L Logic LOW represents rising edge 3 Devi...

Page 11: ...nly the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1513V18 only the upper byte D 17 9 is written into the device D 8 0 remains unaltered H L L H During the data portion...

Page 12: ...nly the byte D 17 9 is written into the device D 8 0 and D 35 18 remains unaltered H L H H L H During the Data portion of a write sequence only the byte D 17 9 is written into the device D 8 0 and D 3...

Page 13: ...g edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Co...

Page 14: ...y scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD p...

Page 15: ...roller follows 11 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCA...

Page 16: ...IGH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 Inst...

Page 17: ...DIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Fig...

Page 18: ...uction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO Th...

Page 19: ...8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15...

Page 20: ...k K K for 1024 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at frequencies do...

Page 21: ...HIGH Voltage Note 18 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 19 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Vol...

Page 22: ...ic 300MHz x8 400 mA x9 400 x18 400 x36 400 278MHz x8 390 mA x9 390 x18 390 x36 390 250MHz x8 380 mA x9 380 x18 380 x36 380 200MHz x8 360 mA x9 360 x18 360 x36 360 167MHz x8 340 mA x9 340 x18 340 x36 3...

Page 23: ...unction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 16 3 C W JC Thermal Resistance Junction to Case 2 1 C W Fig...

Page 24: ...RPS WPS 0 4 0 4 0 5 0 6 0 7 ns tSCDDR tIVKH Double Data Rate Control Setup to Clock K K Rise BWS0 BWS1 BWS2 BWS3 0 3 0 3 0 35 0 4 0 5 ns tSD 25 tDVKH D X 0 Setup to Clock K K Rise 0 3 0 3 0 35 0 4 0...

Page 25: ...Clock C C Rise to High Z Active to High Z 26 27 0 45 0 45 0 45 0 45 0 50 ns tCLZ tCHQX1 Clock C C Rise to Low Z 26 27 0 45 0 45 0 45 0 45 0 50 ns DLL Timing tKC Var tKC Var Clock Phase Jitter 0 20 0 2...

Page 26: ...D tCLZ DOH tCHZ t t tKL tCYC tCCQO t CCQO tCQOH tCQOH KHKH KH Q00 Q03 Q01 Q02 Q20 Q23 Q21 Q22 tCO tCQDOH t D10 D11 D12 D13 t SD tHD tSD tHD D30 D31 D32 D33 Notes 28 Q00 refers to output from address A...

Page 27: ...65 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1526V18 300BZI CY7C1513V18 300BZI CY7C1515V18 300BZI CY7C1511V18 300BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 m...

Page 28: ...250BZXI 200 CY7C1511V18 200BZC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Commercial CY7C1526V18 200BZC CY7C1513V18 200BZC CY7C1515V18 200BZC CY7C1511V18 200BZXC 51 85195 165 Ball...

Page 29: ...18 167BZXC CY7C1511V18 167BZI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1526V18 167BZI CY7C1513V18 167BZI CY7C1515V18 167BZI CY7C1511V18 167BZXI 51 85195 165 Ball Fi...

Page 30: ...3V18 CY7C1515V18 Document Number 38 05363 Rev F Page 30 of 32 Package Diagram Figure 6 165 ball FBGA 15 x 17 x 1 4 mm 51 85195 0 2 2 8 8 8 3 4 0 0 2 2 4 0 6 7 44 6 7 0 2 0 2 3 2 0 490 3 2 3 3 4 3 0 7...

Page 31: ...nal Added CY7C1526V18 part number to the title Added 278 MHz speed Bin Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Changed C C Pin...

Page 32: ...above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE...

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