Cypress Semiconductor CY7C1330AV25 Specification Sheet Download Page 11

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PRELIMINARY

CY7C1330AV25
CY7C1332AV25

Document No: 001-07844 Rev. *A

Page 11 of 19

Scan Register Sizes

Register Name

Bit Size—CY7C1330AV25

Bit Size—CY7C1332AV25

Instruction

Bypass

Boundary Scan

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the Input/Output ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

100

Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

RESERVED

110

Do Not Use: This instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.

Boundary Scan Order (1 Mbit x 18)

Bit #

Bump ID

Bit #

Bump ID

Bit #

Bump ID

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Summary of Contents for CY7C1330AV25

Page 1: ...d with late write operation These SRAMs can achieve speeds up to 250 MHz Each memory cell consists of six transistors Late write feature avoids an idle cycle required during the turnaround of the bus...

Page 2: ...REF VSS VSS VSS VSS M1 CE VSS OE VSS VDDQ BWSc NC VSS NC VDDQ VDD VREF VDD VSS K K BWSa WE VSS VDDQ VSS ZZ NC NC A A A0 A1 VSS VDD M2 CY7C1330AV25 512K x 36 DQc DQb A DQc DQb DQc DQc DQc DQb DQb DQa D...

Page 3: ...n HIGH DQa DQd are placed in a tri state condition The outputs are automatically tri stated during the data portion of a write sequence during the first clock when emerging from a deselected state and...

Page 4: ...ss is initiated when the following conditions are satisfied at clock rise 1 CE is asserted active and 2 the write signal WE is asserted LOW The address presented to Ax is loaded into the Address Regis...

Page 5: ...V25 WE BWd BWc BWb BWa Read 1 X X X X Write Byte 0 DQa 0 1 1 1 0 Write Byte 1 DQb 0 1 1 0 1 Write Bytes 1 0 0 1 1 0 0 Write Byte 2 DQc 0 1 0 1 1 Write Bytes 2 0 0 1 0 1 0 Write Bytes 2 1 0 1 0 0 1 Wri...

Page 6: ...CK Data is output on the TDO pin on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed b...

Page 7: ...y up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an inpu...

Page 8: ...the value at TMS at the rising edge of TCK TAP Controller State Diagram 6 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR SELECT IR SCAN CAPTUR...

Page 9: ...Clock LOW 20 ns Set up Times tTMSS TMS Set up to TCK Clock Rise 5 ns tTDIS TDI Set up to TCK Clock Rise 5 ns tCS Capture Set up to TCK Rise 5 ns Hold Times tTMSH TMS Hold after TCK Clock Rise 5 ns tT...

Page 10: ...F Z0 50 GND 1 25V 50 2 5V 0V ALL INPUT PULSES 1 25V Test Clock Test Mode Select TCK TMS Test Data In TDI Test Data Out tTCYC tTMSH tTL tTH tTMSS tTDIS tTDIH tTDOV tTDOX TDO Identification Register Def...

Page 11: ...11 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the Input Output ring contents Places the boundary scan register between TDI and TDO Does not affect the SRAM oper...

Page 12: ...T 27 6E 51 3G 4 6R 28 7D 52 4D 5 5T 29 6D 53 4E 6 7T 30 6A 54 4G 7 6P 31 6C 55 4H 8 7P 32 5C 56 4M 9 6N 33 5A 57 3L 10 7N 34 6B 58 1K 11 6M 35 5B 59 2K 12 6L 36 3B 60 1L 13 7L 37 2B 61 2L 14 6K 38 3A...

Page 13: ...Impedance Mode 15 VSS 0 2 V VOH3 Output HIGH Voltage IOH 6 0 mA Minimum Impedance Mode 15 VDDQ 0 4 VDDQ V VOL3 Output LOW Voltage IOL 6 0 mA Minimum Impedance Mode 15 VSS 0 4 V VIH Input HIGH Voltage...

Page 14: ...a of AC Test Loads Capacitance 17 Parameter Description Test Conditions Max Unit CIN Input Capacitance TA 25 C f 1 MHz VDD 2 5V VDDQ 1 5V 5 pF CCLK Clock Input Capacitance 6 pF CI O Input Output Capa...

Page 15: ...et Up Before CLK Rise 0 3 0 3 ns tCES Chip Select Set Up 0 3 0 3 ns Hold Times tAH Address Hold After CLK Rise 0 6 0 6 ns tDH Data Input Hold After CLK Rise 0 6 0 6 ns tWEH WE BWx Hold After CLK Rise...

Page 16: ...elect the device Any chip enable can deselect the device 25 RAx stands for Read Address X WAx Write Address X Dx stands for Data in for location X Qx stands for Data out for location X 26 CE held LOW...

Page 17: ...orms continued CLK CE tCYC tCH tCL tCES tCEH DON T CARE UNDEFINED READ WRITE READ DESELECT WRITE Deselect READ WRITE WRITE DESELECT ADDRESS WE Data In Out RA1 tAH tAS tWEStWEH tCO Q1 Out D2 In WA2 WA5...

Page 18: ...s in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges All product and company names mentioned in this...

Page 19: ...Document Title CY7C1330AV25 CY7C1332AV25 18 Mbit 512K x 36 1Mbit x 18 Pipelined Register Register Late Write SRAM Document Number 001 07844 REV ECN No Issue Date Orig of Change Description of Change...

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