Cypress Semiconductor CY7C1324H Specification Sheet Download Page 10

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CY7C1324H

Document #: 001-00208 Rev. *B

Page 10 of 15

Timing Diagrams

Read Cycle Timing

[15]

Note:

15. On this diagram, when CE is LOW, CE

is LOW, CE

is HIGH and CE

is LOW. When CE is HIGH, CE

is HIGH or CE

is LOW or CE

is HIGH.

tCYC

CLK

tADH

tADS

ADDRESS

tAH

tAS

tCEH

tCES

Data Out (Q)

High-Z

tCLZ

tDOH

tCDV

tOEHZ

tCDV

Single READ

BURST

READ

tOEV

tOELZ

tCHZ

Burst wraps around
to its initial state

ADVH

ADVS

WEH

WES

tADH

tADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1)

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

ADV suspends burst.

Deselect Cycle

DON’T CARE

UNDEFINED

ADSP

ADSC

GW, BWE,BW

[A:B]

ADV

[+] Feedback

Summary of Contents for CY7C1324H

Page 1: ...Burst Control inputs ADSC ADSP and ADV Write Enables BW A B and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin The CY7C1324H allows either interleaved or linea...

Page 2: ...C VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW A CE 3 V DD V SS CLK GW BWE OE ADSP A...

Page 3: ...le when emerging from a deselected state ADV Input Synchronous Advance Input signal sampled on the rising edge of CLK When asserted it automatically increments the address in a burst cycle ADSP Input...

Page 4: ...ce Byte Writes are allowed During Byte Writes BWA controls DQA and BWB controls DQB All I Os are tri stated during a Byte Write Since this is a common I O device the asynchronous OE input signal must...

Page 5: ...ontinue Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cycle Continue Burst Next H X X...

Page 6: ...001 00208 Rev B Page 6 of 15 Truth Table for Read Write 2 3 Function GW BWE BWB BWA Read H H X X Read H L H H Write Byte A DQPA H L H L Write Byte B DQPB H L L H Write All Bytes H L L L Write All Byte...

Page 7: ...Voltage for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V VIL Input LOW Voltage 6 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Cu...

Page 8: ...llow standard test methods and proce dures for measuring thermal impedance per EIA JESD51 30 32 C W JC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Notes 8 Tested initially...

Page 9: ...CLK Rise 0 5 ns tWEH GW BWE BW A B Hold after CLK Rise 0 5 ns tADVH ADV Hold after CLK Rise 0 5 ns tDH Data Input Hold after CLK Rise 0 5 ns tCEH Chip Enable Hold after CLK Rise 0 5 ns Notes 9 Timing...

Page 10: ...CE2 is LOW or CE3 is HIGH tCYC tCL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES Data Out Q High Z tCLZ tDOH tCDV tOEHZ tCDV Single READ BURST READ tOEV tOELZ tCHZ Burst wraps around to its initial...

Page 11: ...ESS t CH tAH tAS A1 tCEH tCES High Z BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADVS tWEH...

Page 12: ...cle is performed 18 GW is HIGH Timing Diagrams continued tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A2 tCEH tCES Single WRITE D A3 A3 A4 BURST READ Back to Back READs High Z Q A2 Q A4 Q A4 1 Q A4 2...

Page 13: ...n entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 20 DQs are in High Z when exiting ZZ sleep mode Timing Diagrams continued t ZZ I SUPPLY CLK ZZ...

Page 14: ...a trademark of Intel Corporation All product and company names mentioned in this document may be the trademarks of their respective holders Ordering Information Not all of the speed package and tempe...

Page 15: ...r Corporation on Page 1 from 3901 North First Street to 198 Champion Court Removed 100 MHz Speed bin Changed Three State to Tri State Modified Input Load to Input Leakage Current except ZZ and MODE in...

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