CY7C1246V18, CY7C1257V18
CY7C1248V18, CY7C1250V18
36-Mbit DDR-II+ SRAM 2-Word
Burst Architecture (2.0 Cycle Read Latency)
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-06348 Rev. *D
Revised March 11, 2008
Features
■
36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
■
300 MHz to 375 MHz clock for high bandwidth
■
2-Word burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces
(data transferred at 750 MHz) at 375 MHz
■
Read latency of 2.0 clock cycles
■
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
■
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■
Data valid pin (QVLD) to indicate valid data on the output
■
Synchronous internally self-timed writes
■
Core V
DD
= 1.8V ± 0.1V; IO V
DDQ
= 1.4V to V
DD
[1]
■
HSTL inputs and variable drive HSTL output buffers
■
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
■
Offered in both in Pb-free and non Pb-free packages
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1246V18 – 4M x 8
CY7C1257V18 – 4M x 9
CY7C1248V18 – 2M x 18
CY7C1250V18 – 1M x 36
Functional Description
The CY7C1246V18, CY7C1257V18, CY7C1248V18, and
CY7C1250V18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of both K and K. Each address location is associated with two
8-bit words (CY7C1246V18), 9-bit words (CY7C1257V18),
18-bit words (CY7C1248V18), or 36-bit words (CY7C1250V18)
that burst sequentially into or out of the device.
Asynchronous inputs include output impedance matching input
(ZQ). Synchronous data outputs (Q, which share the same
physical pins with the data inputs, D) are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from individual DDR SRAMs in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Description
375 MHz
333 MHz
300 MHz
Unit
Maximum Operating Frequency
375
333
300
MHz
Maximum Operating Current
1210
1080
1000
mA
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
V
DDQ
= 1.4V to V
DD
.
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