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Document Number: 001-06365 Rev. *D

Revised March 12, 2008

Page 28 of 28

QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All
product and company names mentioned in this document are the trademarks of their respective holders.

CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18

© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress. 

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges. 

Use may be limited by and subject to the applicable Cypress software license agreement. 

Document History Page

Document Title: CY7C1241V18/CY7C1256V18/CY7C1243V18/CY7C1245V18,  36-Mbit QDR™-II+ SRAM 4-Word Burst 
Architecture (2.0 Cycle Read Latency) 
Document Number:

 

001-06365

 

REV.

ECN NO.

ISSUE 

DATE

ORIG. OF 
CHANGE

DESCRIPTION OF CHANGE

**

425689

See ECN

NXR

New Data Sheet

*A

461639

See ECN

NXR

Revised the MPNs from 
CY7C1256AV18 to CY7C1256V18
CY7C1243AV18 to CY7C1243V18
CY7C1245AV18 to CY7C1245V18
Changed t

TH 

and t

TL 

from 40 ns to 20 ns, changed t

TMSS

, t

TDIS

, t

CS

t

TMSH

, t

TDIH

, t

CH 

from

 

10 ns to 5 ns and changed t

TDOV 

from 20 ns to 10 

ns in TAP AC Switching Characteristics table 
Modified Power-Up waveform

*B

497628

See ECN

NXR

Changed the V

DDQ

 operating voltage to 1.4V to V

DD

 in the Features 

section, in Operating Range table and in the DC Electrical Characteristics 
table
Added foot note in page# 1
Changed the Maximum rating of Ambient Temperature with Power 
Applied from –10°C to +85°C to –55°C to +125°C 
Changed V

REF

 (Max.) spec from 0.85V to 0.95V in the DC Electrical 

Characteristics table and in the note below the table
Updated footnote #20 to specify Overshoot and Undershoot Spec
Updated 

Θ

JA 

and 

Θ

JC 

values

Removed x9 part and its related information
Updated footnote #25

*C

1072841

See ECN

VKN/KKVTMP Converted from preliminary to final

Added x8 and x9 parts
Changed I

DD

 values from 950 mA to 1240 mA for 375 MHz, 850 mA to 

1120 mA for 333 MHz, 800 mA to 1040 mA for 300 MHz
Changed I

SB

 values from 300 mA to 310 mA for 375 MHz, 275 mA to 300 

mA for 333 MHz, 250 mA to 280 mA for 300 MHz
Changed t

CYC

 max spec to 8.4 ns for all speed bins

Changed 

Θ

JA

 value from 12.43 °C/W to 16.25 °C/W

Updated Ordering Information table

*D

2198506

See ECN

VKN/AESA

Added footnote# 21related to I

DD

[+] Feedback 

[+] Feedback 

Summary of Contents for CY7C1241V18

Page 1: ...e QDR II architecture consists of two separate ports to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to supp...

Page 2: ...ister Reg Reg Reg 16 20 8 32 8 NWS 1 0 VREF Write Add Decode Write Reg 16 A 19 0 20 1M x 8 Array 1M x 8 Array 1M x 8 Array Write Reg Write Reg Write Reg 8 CQ CQ DOFF QVLD 1M x 9 Array CLK A 19 0 Gen K...

Page 3: ...Reg 36 19 18 72 18 BWS 1 0 VREF Write Add Decode Write Reg 36 A 18 0 19 512K x 18 Array 512K x 18 Array 512K x 18 Array Write Reg Write Reg Write Reg 18 CQ CQ DOFF QVLD 256K x 36 Array CLK A 17 0 Gen...

Page 4: ...C VSS NC Q2 NC NC NC VREF NC NC VDDQ NC VDDQ NC NC VDDQ VDDQ VDDQ D1 VDDQ NC Q1 NC VDDQ VDDQ NC VSS NC D0 NC TDI TMS VSS A NC A NC D2 NC ZQ NC Q0 NC NC NC NC A NC 144M CY7C1256V18 4M x 9 2 3 4 5 6 7 1...

Page 5: ...D5 NC NC VREF NC Q3 VDDQ NC VDDQ NC Q5 VDDQ VDDQ VDDQ D4 VDDQ NC Q4 NC VDDQ VDDQ NC VSS NC D2 NC TDI TMS VSS A NC A D7 D6 NC ZQ D3 Q2 D1 Q1 D0 NC A NC CY7C1245V18 1M x 36 2 3 4 5 6 7 1 A B C D E F G H...

Page 6: ...ss Inputs Sampled on the rising edge of the K clock during active read and write opera tions These address inputs are multiplexed for both read and write operations Internally the device is organized...

Page 7: ...is pin to ground turns off the DLL inside the device The timing in the DLL turned off operation is different from that listed in this data sheet For normal operation this pin can be connected to a pul...

Page 8: ...ing edge of the Positive Input Clock K This enables a seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiate...

Page 9: ...generated by the QDR II CQ is referenced with respect to K and CQ is refer enced with respect to K These are free running clocks and are synchronized to the input clock of the QDR II The timing for t...

Page 10: ...D A K SRAM 4 RQ 250ohms ZQ CQ CQ Q K RPS WPS BWS D A K SRAM 1 RQ 250ohms ZQ CQ CQ Q K RPS WPS BWS RPS WPS BWS R 50ohms Vt V 2 DDQ R Notes 2 X Don t Care H Logic HIGH L Logic LOW represents rising edg...

Page 11: ...7C1241V18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1243V18 only the upper byte D 17 9 is written into the device D 8 0 remains unaltered H L L H During the da...

Page 12: ...y the byte D 17 9 is written into the device D 8 0 and D 35 18 remain unaltered H L H H L H During the data portion of a write sequence only the byte D 17 9 is written into the device D 8 0 and D 35 1...

Page 13: ...lling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TA...

Page 14: ...egister After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an...

Page 15: ...3V18 and CY7C1245V18 follows 11 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR SELECT IR SCAN CAPTURE IR SHIFT IR EXIT1 IR PAUSE IR EXIT2 IR U...

Page 16: ...GH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 Instr...

Page 17: ...MSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invali...

Page 18: ...struction Codes Instruction Code Description EXTEST 000 Captures the input output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO Thi...

Page 19: ...35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M...

Page 20: ...e power and clock K K for 2048 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions a...

Page 21: ...A Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltage IOL 0 1 mA Nominal Impedance VSS 0 2 V VIH Input HIGH Voltage VREF 0 1 VDDQ 0 15 V VIL Input LOW Voltage 0 15 VREF 0 1 V IX Input Leakage...

Page 22: ...Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 16 25 C W JC Thermal Resistance Junction to Case 2 91 C W AC Test Loads and Waveforms...

Page 23: ...2 0 2 ns tCQDOH tCQHQX Echo Clock High to Data Invalid 0 2 0 2 0 2 ns tCQH tCQHCQL Output Clock CQ CQ HIGH 25 0 88 1 03 1 15 ns tCQHCQH tCQHCQH CQ Clock Rise to CQ Clock Rise 25 rising edge to rising...

Page 24: ...A WPS RPS K K DON T CARE UNDEFINED CQ CQ tCQOH CCQO t tCQOH CCQO t tQVLD QVLD tQVLD Read Latency 2 0 Cycles CLZ t t CO tDOH tCQDOH CQD t tCHZ Q00 Q01 Q20 Q02 Q21 Q03 Q22 Q23 tCQH tCQHCQH Q Notes 30 Q...

Page 25: ...all Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1256V18 375BZI CY7C1243V18 375BZI CY7C1245V18 375BZI CY7C1241V18 375BZXI 51 85195 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb...

Page 26: ...0BZXC CY7C1241V18 300BZI 51 85195 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1256V18 300BZI CY7C1243V18 300BZI CY7C1245V18 300BZI CY7C1241V18 300BZXI 51 85195 165 ball Fine Pi...

Page 27: ...Y7C1245V18 Document Number 001 06365 Rev D Page 27 of 28 Package Diagram Figure 5 165 ball FBGA 15 x 17 x 1 40 mm 51 85195 0 2 2 8 8 8 3 4 0 0 2 2 4 0 6 7 44 6 7 0 2 0 2 3 2 0 490 3 2 3 3 4 3 0 7 4 G...

Page 28: ...LIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any...

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