CY7C1041DV33
Document #: 38-05473 Rev. *E
Page 6 of 13
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
[14]
Min
Max
Unit
V
DR
V
CC
for Data Retention
2.0
V
I
CCDR
Data Retention Current
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
Ind’l
10
mA
Auto
15
mA
t
CDR
[6]
Chip Deselect to Data Retention Time
0
ns
t
R
[15]
Operation Recovery Time
t
RC
ns
Data Retention Waveform
3.0V
3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
Switching Waveforms
Figure 4. Read Cycle No. 1
[16, 17]
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
Notes
12. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write and the transition of either of
these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
13. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
14. No input may exceed V
CC
+ 0.3V.
15. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 50
μ
s or stable at V
CC(min.)
> 50
μ
s.
16. Device is continuously selected. OE, CE, BHE, and BHE = V
IL
.
17. WE is HIGH for read cycle.
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