Cypress Semiconductor CY7C027AV Specification Sheet Download

Page: 16 / 18

CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

Document #: 38-06078 Rev. *B

Page 16 of 18

Ordering Information

32K x16 3.3V Asynchronous Dual-Port SRAM

Speed

(ns)

Ordering Code

Package

Name

Package Type

Operating

Range

CY7C027V-15AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C027V-15AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

CY7C027VN-15AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

CY7C027V-20AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C027V-20AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

CY7C027V-25AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C027V-25AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

CY7C027AV-25AXI

A100

100-Pin Pb-Free Thin Quad Flat Pack

Industrial

64K x16 3.3V Asynchronous Dual-Port SRAM

Speed

(ns)

Ordering Code

Package

Name

Package Type

Operating

Range

CY7C028V-15AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C028V-15AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

CY7C028V-20AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C028V-20AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

CY7C028V-20AI

A100

100-Pin Thin Quad Flat Pack

Industrial

CY7C028V-20AXI

A100

100-Pin Pb-Free Thin Quad Flat Pack

Industrial

CY7C028V-25AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C028V-25AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

32K x18 3.3V Asynchronous Dual-Port SRAM

Speed

(ns)

Ordering Code

Package

Name

Package Type

Operating

Range

CY7C037V-15AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C037V-15AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

CY7C037V-20AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C037AV-20AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

CY7C037V-25AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C037V-25AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

64K x18 3.3V Asynchronous Dual-Port SRAM

Speed

(ns)

Ordering Code

Package

Name

Package Type

Operating

Range

CY7C038V-15AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C038V-15AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

CY7C038V-20AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C038V-20AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

CY7C038V-20AI

A100

100-Pin Thin Quad Flat Pack

Industrial

CY7C038V-20AXI

A100

100-Pin Pb-Free Thin Quad Flat Pack

Industrial

CY7C038V-25AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C038V-25AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

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Summary of Contents for CY7C027AV

Page 1: ...software handshaking between ports INT flag for port to port communication Separate upper byte and lower byte control Dual chip enables Pin select for Master or Slave Commercial and Industrial temperature ranges 100 pin Pb free TQFP and 100 pin TQFP Notes 1 CY7C027V CY7C027VN and CY7C027AV are functionally identical 2 CY7C037V and CY7C037AV are functionally identical 3 I O8 I O15 for x16 devices I...

Page 2: ...51 CY7C027V 027VN 027AV 32K x 16 A9L A10L A11L A12L A13L A14L UBL NC LBL CE1L SEML OEL GND NC A15L VCC R WL GND I O15L I O14L I O13L I O12L I O11L I O10L CE0L 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 A8L A7L A6L A5L A4L A3L INTL A1L NC GND M S A0R A1R A0L A2L BUSYR INTR A2R A3R A4R A5R A6R A7R A8R BUSYL 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 NC I O9R I O8R I O7R VCC ...

Page 3: ...I O14L I O13L I O12L I O11L I O10L SEML 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 A8L A7L A6L A5L A4L A3L BUSYL A1L INTL GND VCC INTR A0R A0L A2L M S BUSYR A1R A2R A3R A4R A5R A6R A7R GND 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 I O10R I O9R I O8R I O7R VCC I O6R I 01R I O4R I O2R GND I O0L I O2L I O3L I O3R I O5R I O1L GND I O4L I O5L I O6L I O7L VCC I O8L I O9L I O0R ...

Page 4: ...n from one port to the other to indicate that a shared resource is in use The semaphore logic is comprised of eight shared latches Only one side can control the latch semaphore at any time Control of a semaphore indicates that a shared resource is in use An automatic power down feature is controlled independently on each port by a chip select CE pin The CY7C027V 027VN 027AV 028V and CY7037V 037AV ...

Page 5: ... between the two ports The state of the semaphore indicates that a resource is in use For example if the left port wants to request a given resource it sets a latch by writing a zero to a semaphore location The left port then verifies its success in setting the latch by reading it After writing to the semaphore SEM or OE must be deasserted for tSOP before attempting to read the semaphore The semap...

Page 6: ...2 2 V VIL Input LOW Voltage 0 8 0 8 0 8 V IIX Input Leakage Current 5 5 5 5 5 5 μA IOZ Output Leakage Current 10 10 10 10 10 10 μA ICC Operating Current VCC Max IOUT 0 mA Outputs Disabled Com l 125 185 120 175 115 165 mA Ind 3 140 195 mA ISB1 Standby Current Both Ports TTL Level CEL CER VIH f fMAX Com l 35 50 35 45 30 40 mA Ind 3 45 55 mA ISB2 Standby Current One Port TTL Level CEL CER VIH f fMAX ...

Page 7: ... to High Z 10 12 15 ns tPU 10 CE LOW to Power Up 0 0 0 ns tPD 10 CE HIGH to Power Down 15 20 25 ns tABE 7 Byte Enable Access Time 15 20 25 ns Write Cycle tWC Write Cycle Time 15 20 25 ns tSCE 7 CE LOW to Write End 12 16 20 ns tAW Address Valid to Write End 12 16 20 ns tHA Address Hold From Write End 0 0 0 ns tSA 7 Address Setup to Write Start 0 0 0 ns tPWE Write Pulse Width 12 17 22 ns tSD Data Se...

Page 8: ... 20 20 ns tBHC BUSY HIGH from CE HIGH 15 16 17 ns tPS Port Setup for Priority 5 5 5 ns tWB R W HIGH after BUSY Slave 0 0 0 ns tWH R W HIGH after BUSY HIGH Slave 13 15 17 ns tBDD 13 BUSY HIGH to Data Valid 15 20 25 ns Interrupt Timing 11 tINS INT Set Time 15 20 20 ns tINR INT Reset Time 15 20 20 ns Semaphore Timing tSOP SEM Flag Update Pulse OE or SEM 10 10 12 ns tSWRD SEM Flag Write to Read Time 5...

Page 9: ...ransition LOW 19 To access RAM CE VIL UB or LB VIL SEM VIH To access semaphore CE VIH SEM VIL tRC tAA tOHA DATA VALID PREVIOUS DATAVALID DATA OUT ADDRESS tOHA Figure 4 Read Cycle No 1 Either Port Address Access 15 16 17 tACE tLZOE tDOE tHZOE tHZCE DATA VALID tLZCE tPU tPD ISB ICC DATA OUT OE CE and LB or UB CURRENT Figure 5 Read Cycle No 2 Either Port CE OE Access 15 18 19 UB or LB DATA OUT tRC AD...

Page 10: ...hort as the specified tPWE 24 To access RAM CE VIL SEM VIH 25 To access upper byte CE VIL UB VIL SEM VIH To access lower byte CE VIL LB VIL SEM VIH 26 Transition is measured 500 mV from steady state with a 5 pF load including scope and jig This parameter is sampled and not 100 tested 27 During this period the I O pins are in the output state and input signals must not be applied 28 If the CE or SE...

Page 11: ...olated the semaphore is definitely obtained by one side or the other but which side gets the semaphore is unpredictable Switching Waveforms continued tSOP tSAA VALID ADRESS VALID ADRESS tHD DATAIN VALID DATAOUT VALID tOHA tAW tHA tACE tSOP tSCE tSD tSA tPWE tSWRD tDOE WRITE CYCLE READ CYCLE OE R W I O 0 SEM 0 A 2 Figure 9 Semaphore Read After Write Timing Either Side 29 A MATCH tSPS A0L A2L MATCH ...

Page 12: ... CEL CER LOW Switching Waveforms continued VALID tDDD tWDD MATCH MATCH R WR DATA INR DATAOUTL tWC ADDRESSR tPWE VALID tSD tHD ADDRESSL tPS tBLA tBHA tBDD BUSYL Figure 11 Timing Diagram of Read with BUSY M S HIGH 33 tPWE R W BUSY tWB tWH Figure 12 Write Timing with Busy Input M S LOW Feedback ...

Page 13: ... MATCH tPS tBLC tBHC ADDRESS MATCH tPS tBLC tBHC CER ValidFirst ADDRESS L R BUSYR CEL CER BUSYL CER CEL ADDRESSL R Figure 13 Busy Timing Diagram No 1 CE Arbitration 34 CELValid First ADDRESS MATCH tPS ADDRESSL BUSYR ADDRESS MISMATCH tRC or tWC tBLA tBHA ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL BUSYL tRC or tWC tBLA tBHA ADDRESSR Right Address Valid First Figure 14 Busy Timing Diagram N...

Page 14: ... R WL is asserted last Switching Waveforms continued WRITE 7FFF FFFF for CY7C028V 38V tWC Right Side Clears INTR tHA READ 7FFF tRC tINR WRITE 7FFE FFFE for CY7C028V 38V tWC Right Side Sets INTL Left Side Sets INTR Left Side Clears INT L READ 7FFE tINR tRC ADDRESSR CE L R W L INT L OE L ADDRESSR R WR CER INTL ADDRESSR CER R WR INTR OE R ADDRESSL R WL CEL INTR tINS tHA tINS FFFF for CY7C028V 38V FFF...

Page 15: ...ight Port Function R WL CEL OEL A0L 14L INTL R WR CER OER A0R 14R INTR Set Right INTR Flag L L X 7FFF X X X X X L 39 Reset Right INTR Flag X X X X X X L L 7FFF H 38 Set Left INTL Flag X X X X L 38 L L X 7FFE X Reset Left INTL Flag X L L 7FFE H 39 X X X X X Table 3 Semaphore Operation Example Function I O0 I O17 Left I O0 I O17 Right Status No action 1 1 Semaphore free Left port writes 0 to semapho...

Page 16: ... Flat Pack Industrial CY7C028V 20AXI A100 100 Pin Pb Free Thin Quad Flat Pack Industrial 25 CY7C028V 25AC A100 100 Pin Thin Quad Flat Pack Commercial CY7C028V 25AXC A100 100 Pin Pb Free Thin Quad Flat Pack Commercial 32K x18 3 3V Asynchronous Dual Port SRAM Speed ns Ordering Code Package Name Package Type Operating Range 15 CY7C037V 15AC A100 100 Pin Thin Quad Flat Pack Commercial CY7C037V 15AXC A...

Page 17: ...CY7C027V 027VN 027AV 028V CY7C037V 037AV 038V Document 38 06078 Rev B Page 17 of 18 Package Diagram Figure 16 100 Pin Pb Free Thin Plastic Quad Flat Pack TQFP A100 51 85048 C Feedback ...

Page 18: ...e express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of th...

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