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Document #: 38-05684 Rev. *D

Revised June 16, 2008

Page 10 of 10

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CY62158E MoBL

®

© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
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application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 

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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges. 

Use may be limited by and subject to the applicable Cypress software license agreement. 

Document History Page

Document Title: CY62158E MoBL

®

 8-Mbit (1M x 8) Static RAM

Document Number: 38-05684

REV.

ECN NO.

Issue Date

Orig. of 

Change

Description of Change

**

270350

See ECN

PCI

New Data Sheet

*A

291271

See ECN

SYT

Converted from Advance Information to Preliminary
Changed input pulse level from V

CC

 to 3V in the AC Test Loads and Waveforms

Modified footnote #9 to include timing reference level of 1.5V and input pulse 
level of 3V

*B

1462592

See ECN

VKN/AESA Converted from preliminary to final

Removed 35 ns speed bin
Removed “L” parts
Removed 48-Ball VFBGA package
Changed I

CC(max)

 spec from 2.3 mA to 3 mA at f=1 MHz

Changed I

CC(typ)

 spec from 16 mA to 18 mA at f=f

MAX

Changed I

CC(max)

 spec from 28 mA to 25 mA at f=f

MAX

Changed I

SB1(typ)

 and I

SB2(typ) 

spec from 0.9 

μ

A to 2 

μ

Changed I

SB1(max)

 and I

SB2(max) 

spec from 4.5 

μ

A to 8 

μ

A

Changed I

CCDR(max)

 spec from 4.5 

μ

A to 8 

μ

A

Changed t

LZOE

 spec from 3 ns to 5 ns

Changed t

LZCE

 spec from 6 ns to 10 ns

Changed t

HZCE

 spec from 22 ns to 18 ns

Changed t

PWE

 spec from 30 ns to 35 ns

Changed t

SD

 spec from 22 ns to 25 ns

Changed t

LZWE

 spec from 6 ns to 10 ns

Added footnote# 6 related to I

SB2

 and I

CCDR

Updated Ordering information table

*C

2428708

See ECN

VKN/PYRS Corrected typo in the Ordering Information table

*D

2516494

See ECN 

PYRS

Corrected ECN number

[+] Feedback 

Summary of Contents for CY62158E

Page 1: ...e device into standby mode reduces power consumption significantly when deselected CE1 HIGH or CE2 LOW To write to the device take Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW Data...

Page 2: ...5 1 8 3 18 25 2 8 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 A5 18 17 20 19 23 28 25 24 22 21 27 26 A6 A7 A4 A3 A2 A1 A0 A17 A18 A10 A11 A12 A13 A15 A16 A14 OE...

Page 3: ...rrent f fMAX 1 tRC VCC VCCmax IOUT 0 mA CMOS levels 18 25 mA f 1 MHz 1 8 3 mA ISB1 Automatic CE Power down Current CMOS Inputs CE1 VCC 0 2V CE2 0 2V VIN VCC 0 2V VIN 0 2V f fMAX Address and Data Only...

Page 4: ...V 8 A tCDR 7 Chip Deselect to Data Retention Time 0 ns tR 8 Operation Recovery Time tRC ns Figure 3 Data Retention Waveform 3V VCC OUTPUT R2 100 pF INCLUDING JIG AND SCOPE GND 90 10 90 10 Rise Time 1...

Page 5: ...ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE WE LOW to High Z 10 11 18 ns tLZWE WE HIGH to Low Z 10 10 ns Notes 9 Test conditions for all parameters other than tri stat...

Page 6: ...14 15 Figure 5 Read Cycle No 2 ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID tRC tAA tOHA 50 50 DATA VALID tRC tACE tDOE tLZOE tLZCE tPU HIGH IMPEDANCE tHZOE tHZCE tPD HIGH ICC ISB IMPEDANCE OE CE1...

Page 7: ...Switching Waveforms continued tHD tSD tPWE tSA tHA tAW tSCE tWC tHZOE VALID DATA NOTE 18 CE1 ADDRESS CE2 WE DATA IO OE tWC VALID DATA tAW tSA tPWE tHA tHD tSD tSCE CE1 ADDRESS CE2 WE DATA IO OE Notes...

Page 8: ...L X X High Z Deselect Power Down Standby ISB L H H L Data Out Read Active ICC L H H H High Z Output Disabled Active ICC L H L X Data in Write Active ICC Ordering Information Speed ns Ordering Code Pa...

Page 9: ...CY62158E MoBL Document 38 05684 Rev D Page 9 of 10 Package Diagrams Figure 9 44 Pin TSOP II 51 85087 51 85087 A Feedback...

Page 10: ...Y KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make ch...

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