SSR/CHS/001
13
Parameter definitions
Packetization Sink
All
Controller Only
Slot 1
Slot 2
Slot 3
Slot 4
All
Selects which modules the packetizer package will
be sent to for transmission or storage.
IRIG-B-In
IRIG-B Input
-
-
The IRIG-B time source input.
RecorderStatus
TTL Output
-
-
The status of the recorder. High indicates an error
condition.
NAME/DESCRIPTION
BASE UNIT
DATA FORMAT
BITS
REGISTER DEFINITION
Global Parameters
DayOfYear
Day of Year, February first is day
32
BitVector
BitVector
16
R[15:0]
R[15:10] Reserved - Reserved for future use.
R[9:0] DayOfYear - Day of Year 1 to 366.
IrigTime48
48-bit wide IRIG time word.
BitVector
BitVector
48
R[47:0]
TimeHi
Hours and minutes at the start of
the acquisition cycle.
BitVector
BitVector
16
R[47:32]
R[15:13] Reserved - Reserved for future use.
R[12:7] Hours - BCD Hours 0 to 23.
R[6:0] Minutes - BCD Minutes 0 to 59.
TimeLo
Seconds and centiseconds at
the start of the acquisition cycle.
Second
BCD
16
R[31:16]
R(15) Reserved
R[14:8] Seconds - Seconds 0 to 59.
R[7:0] Centiseconds - Centiseconds 0 to 99.
TimeMicro
Microseconds at the start of the
acquisition cycle.
Second
BCD
16
R[15:0]
R[15:0] Microseconds - Microseconds 0 to 9999.
StatusTimer
IRIG-B and timer status register.
BitVector
BitVector
16
R[15:0]
R(15) IRIG-BLock - When 1 the IRIG-B decoder is
locked to a valid IRIG-B stream.
R(14) StraightBinarySeconds - Bit 16 (MSB) of the
Straight Binary Seconds decoded from the IRIG-B
stream (see StraightBinarySeconds for bits 15 to 0).
R[13:3] Reserved
R(2) SourcePrimary - When 1 the timer is locked to
the primary timer source.
R(1) TimerLock - When 1 the timer's PLL is in lock
with the input TIME ONE_PPS source.
R(0) BatteryFail - When 1 power-on test fails (battery
voltage is not present or real time clock is not run-
ning).
SETUP DATA
CHOICE
DEFAULT
NOTES