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EBRUARY
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PCI-P0 B
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LOCK
The PMC-605 functions as the PCI-P0 bus clock source when the CLKDIS signal is connected
directly to Ground. The PMC-605 provides a 33 MHz clock source on both SCLK0 and SCLK1.
The PCI-P0 bus clock source is disabled when the CLKDIS signal is connected directly to Vcc.
In this mode the PCI-P0 bus clock needs to be provided from an external source (such as
from a basecard’s 33 MHz clock or another PMC-605). The PCI-P0 clock source is always
received on PCLK0. PCLK1 is only used in systems with more than three slots on the PCI-P0
bus.
The state of the PMC-605’s arbiter function has no affect on clock selection.
Cross Reference
Refer to “Bus Arbiter Jumper Settings” on page 3-2 for information on configuring arbiter
settings when using the PMC-605 with the PCI-P0 Development Backplane (part number
BPL-605-002 or BPL-605-003).
Cross Reference
The CLKDIS signal referred to above is connected to Ground or Vcc via the 2 or 3 slot PCI-
P0 Development Backplane (part number BPL-605-002 or BPL-605-003). See “PCI Bus
Clock Jumper Settings” on page 3-4 for details.
Caution
CLKDIS must not be left open circuit because it is an input to the CPLD which does not have
a pull-up on it. Inputs should not be left floating. The PMC-605 may not be detected by
the host processor if this line is left open.
Also note that there should be only one card on the PCI-P0 bus that provides the clock
source.
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