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Curtiss-Wright PMC-605 User Manual Download Page 10

C

URTISS

-W

RIGHT

 C

ONTROLS

 E

MBEDDED

 C

OMPUTING

809524 R

EVISION

  D F

EBRUARY

 2009

IX

L

IST

 

OF

 T

ABLES

Table 1.1:

Clock Source Configurations .................................................................................. 1-7

Table 1.2:

Local Control and Status Register (LCSR) .............................................................. 1-10

Table 1.3:

Environmental Specification Limits and Ruggedization Levels ................................... 1-12

Table 1.4:

Pn1/Pn2 Pin Assignments .................................................................................... 1-14

Table 1.5:

Pn3 Pin Assignments .......................................................................................... 1-15

Table 1.6:

Pn4 Pin Assignments .......................................................................................... 1-16

Table 1.7:

J1 Test JTAG Port Pin Assignments ....................................................................... 1-17

Table 1.8:

Sample SVME/DMV-179 P0 Connector Pin Assignments ........................................... 1-18

Table 2.1:

Environmental Specification Limits and Ruggedization Levels ..................................... 2-6

Table 2.2:

PMC Site 1: Pin Assignments (Jn1 and Jn2) ............................................................. 2-7

Table 2.3:

PMC Site 1: Pin Assignments (Jn3 and Jn4) ............................................................. 2-8

Table 2.4:

PMC Site 2: Pin Assignments (Jn1 and Jn2) ............................................................. 2-9

Table 2.5:

PMC Site 2: Pin Assignments (Jn3 and Jn4) ........................................................... 2-10

Table 2.6:

VME P0 Connector Pin Assignments ...................................................................... 2-11

Table 2.7:

Pin Assignments for VME P1 Connector ................................................................. 2-12

Table 2.8:

Pin Assignments for VME P2 Connector ................................................................. 2-13

Table 3.1:

Bus Arbiter Jumper Settings .................................................................................. 3-3

Table 3.2:

PCI Bus Clock Jumper Settings .............................................................................. 3-4

Table 3.3:

System Slot Termination Jumper Settings ............................................................... 3-5

Table 3.4:

2 Slot Backplane Configuration Pins........................................................................ 3-7

Table 3.5:

2 Slot Backplane System Slot 0 Pin Assignments ......................................................3-8

Table 3.6:

2 Slot Backplane Peripheral Slot 1 Pin Assignments .................................................. 3-9

Table 3.7:

3 Slot Backplane Configuration Pins...................................................................... 3-10

Table 3.8:

3 Slot Backplane System Slot 0 ........................................................................... 3-11

Table 3.9:

3 Slot Backplane Peripheral Slot 1 ........................................................................ 3-12

Table 3.10:

3 Slot Backplane Peripheral Slot 2 ........................................................................ 3-13

Table 4.1:

Serial EEPROM Factory Default Values..................................................................... 4-4

Table 4.2:

PCI-P0 Configuration Space Address Map .............................................................. 4-12

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Summary of Contents for PMC-605

Page 1: ...utilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of their respective owners...

Page 2: ...ols Embedded Computing 333 Palladium Drive Ottawa Ontario Canada K2V 1A6 613 599 9199 OUTREACH PCI PMC EXPANSION SYSTEM USER S MANUAL 809524 D February 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com ...

Page 3: ...nstalled Updated Table 2 6 to reflect pinout changes signals on P0 connector pins P0 A4 and P0 C4 have been swapped that were introduced via ECO number 500000000673 This ECO allows smart PMC modules installed on the SVME DMV 210 to perform DMA cycles back to the host card Added note on page 3 2 that summarizes which E jumpers on the BPL 605 002 and BPL 605 003 are reserved Improved Figure 3 2 Figu...

Page 4: ... information contained in this document must not be disclosed to others for any purpose nor used for manufacturing purposes without written permission of Curtiss Wright Controls Inc The acceptance of this document will be construed as an acceptance of the foregoing condition Copyright 2009 Curtiss Wright Controls Inc All rights reserved TRADEMARKS PowerPC is a trademark of International Business M...

Page 5: ...PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING IV 809524 VERSION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com ...

Page 6: ...ard 2 1 General Description 2 1 Summary of Features 2 2 PCI P0 Bridge Description 2 3 Configuration 2 3 PCI Signal Environment 2 3 PCI System Reset RST 2 3 PCI Interrupts 2 3 PCI JTAG Test Signals 2 4 PMC Bus Mode Signals 2 4 Physical Electrical and environmental Characteristics 2 5 Dimensions 2 5 Mating Connectors 2 5 Electrical Characteristics 2 6 Environmental Characteristics 2 6 Connector Pin ...

Page 7: ...ridging 4 1 PMC 605 Terminology 4 2 Example Transferring Data Between Two SBCs 4 3 Serial EEPROM Configuration 4 3 SVME DMV 179 GPM Map Command With PMC 605 Installed 4 5 Base Address Register Initialization 4 7 Primary BAR Configuration 4 8 Translated Base Register Configuration 4 9 Address Map for Local PCI and P0 Buses 4 11 Transferring Data 4 11 PCI P0 Configuration Space Addressing 4 12 Addre...

Page 8: ...ram 2 2 Figure 2 3 SVME DMV 210 Physical Layout 2 5 Figure 3 1 PCI P0 Development Backplane Slot Locations 3 Slot Version 3 1 Figure 3 2 Bus Arbiter Jumper Locations 3 3 Figure 3 3 Clock Source Jumper Locations 3 4 Figure 3 4 Bus Termination Jumper Locations 3 6 Figure 4 1 Primary and Secondary PCI Buses 4 2 Figure 4 2 Example System 4 3 Figure 4 3 Local PCI Address Map after BAR Configuration 4 7...

Page 9: ...CI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING VIII 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com ...

Page 10: ... Table 2 5 PMC Site 2 Pin Assignments Jn3 and Jn4 2 10 Table 2 6 VME P0 Connector Pin Assignments 2 11 Table 2 7 Pin Assignments for VME P1 Connector 2 12 Table 2 8 Pin Assignments for VME P2 Connector 2 13 Table 3 1 Bus Arbiter Jumper Settings 3 3 Table 3 2 PCI Bus Clock Jumper Settings 3 4 Table 3 3 System Slot Termination Jumper Settings 3 5 Table 3 4 2 Slot Backplane Configuration Pins 3 7 Tab...

Page 11: ...PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING X 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com ...

Page 12: ...210 Carrier Card Describes the features functions and pin assignments of the SVME DMV 210 Carrier Card Chapter 3 PCI P0 Development Backplane Describes the PMC 605 s PCI P0 2 and 3 slot development backplanes Chapter 4 System Configuration Explains how to program the base address registers of the PMC 605 and lists the default contents of the EEPROM device Appendix A Installation Instructions Expla...

Page 13: ... as IRDY TABLE 1 Typographical Conventions Item Convention Example Keystrokes Keys are listed as they appear on most keyboards surrounded by marks Combinations of key strokes appear within a single set of brackets Type Ctrl Alt C to return to the previous menu Type Esc to exit File Names File names are set in italics Open the file named es h Directory Names Directory names show the full directory ...

Page 14: ...ions The warning icon indicates procedures in the manual that if not carried out or if carried out incorrectly could cause physical injury electrical damage to equipment or a non recoverable corruption of data Warnings include instructions for preventing such damage Please observe warning icons and read the accompanying text completely before carrying out the procedure The caution icon indicates n...

Page 15: ...e you can access additional topics such as Continuum Lifecycle Services Technical Support Professional Services Interoperability Repair and Warranty Software Upgrade Program Lifecycle Support Repair and Warranty Information Curtiss Wright Controls Embedded Computing s standard warranty provides one year coverage of parts and labor and also features A repair turnaround target of 15 business days Re...

Page 16: ... signal processor Interconnecting multiple processor cards via a high speed PCI secondary backplane Providing a private PCI data path to custom I O cards Figure 1 1 shows a sample application of the PMC 605 The two SBCs use the PMC 605 to access each others shared PCI resources while the SVME DMV 210 Carrier Card extends the PCI bus of each single board computer with additional I O capabilities FI...

Page 17: ...ystem Controller Functions Arbiter and Local Control and Status Register Secondary PCI Bus Primary PCI Bus Arbiter Functions Configuration Settings Status LED Serial EEPROM Bridge Configuration JTAG JTAG 3 3V Regulator 5V 3 3V Secondary Bus Primary Bus Control PCI Int Pri D bell Int PCI Int H o s t P C I B u s P 0 P C I B u s Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www ...

Page 18: ...ng to the configuration of its PCI bus clock source System Slot Termination The PMC 605 is dynamically configured during power up or reboot to terminate signals as necessary for the PCI bus when placed in the PCI P0 backplane s System Slot Power Requirements The PCI P0 bus is 3 3 V signalling 5 V tolerant The PMC 605 is powered via the basecard s 5 V rail an on board regulator provides 3 3 V Confi...

Page 19: ...nd supports 32 bit addressing and data transfers The Secondary PCI bus is connected to the host basecard s local PCI bus The Secondary PCI bus runs at 33 MHz and supports 64 bit addressing and data transfers FIGURE 1 3 Primary and Secondary PCI Buses Cross Reference The 21554 responds to Type 0 configuration cycles For information about this device refer to the Intel s Getting Started with the 215...

Page 20: ...ction is disabled the role of REQ0 and GNT0 become reversed The REQ0 pin functions as GNT0 i e becomes the Grant 0 input and the GNT0 pin functions as REQ0 i e becomes the Request 0 output In other words REQn signals are always inputs and GNTn signals are always outputs Figure 1 4 illustrates the function of each signal when the PMC 605 s arbiter function is either enabled or disabled FIGURE 1 4 B...

Page 21: ...iter function has no affect on clock selection Cross Reference Refer to Bus Arbiter Jumper Settings on page 3 2 for information on configuring arbiter settings when using the PMC 605 with the PCI P0 Development Backplane part number BPL 605 002 or BPL 605 003 Cross Reference The CLKDIS signal referred to above is connected to Ground or Vcc via the 2 or 3 slot PCI P0 Development Backplane part numb...

Page 22: ...dary buses of each PMC 605 module operate at the same clock speed Asynchronous System Slot The PMC 605 in the system slot receives a 33 MHz clock source from its host card to provide timing for its secondary side The PMC 605 s primary bus uses a clock source generated by its on board oscillator see Note and routes this second clock over the PCI P0 bus In this configuration the primary and secondar...

Page 23: ...NTA INTERRUPTS The 21554 PCI to PCI Bridge device does not accept interrupts although it may generate them to either the primary bus P0 side or secondary bus host processor side Any P0 bus interrupt is seen directly by the basecard as long as bit D5 of the LCSR is set to a 1 if bit D5 of the LCSR is set to a 0 default then the P0 bus interrupt is withheld from the basecard Interrupts are passed be...

Page 24: ...erate a PCI P0 Reset It can either follow the Reset signal from the host or it can be initiated from the host through software The PMC 605 does not accept resets from the PCI P0 bus regardless of the state of TERMDIS If an external PMC 605 reset is required this must be done via the host basecard s VME interface Basecard PMC 605 21554 CPLD System Slot 0 Peripheral Slot 1 Peripheral Slot 2 Basecard...

Page 25: ...Register LCSR is a byte wide register residing within the address space defined by the PCI Expansion ROM Base Address set within the 21554 PCI to PCI Bridge device The bit definitions of the LCSR are as described in Table 1 2 TABLE 1 2 Local Control and Status Register LCSR D7 D6 D5 D4 D3 D2 D1 D0 Not Used Not Used Host INTA Enable LED Control Arbiter Mode Arbiter Status Clock Source Termina tion ...

Page 26: ...he mating connectors on the PMC 605 FIGURE 1 7 PMC 605 Physical Layout DIMENSIONS The PMC 605 is built on a standard PCI Mezzanine Card PMC Printed Wiring Board PWB and is VITA 20 compliant MATING CONNECTORS The connectors Pn1 Pn2 Pn3 and Pn4 are compliant with IEEE P1386 Pn1 Pn2 Pn3 Pn4 Component Side Solder Side 21554 CPLD J1 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE ww...

Page 27: ...BLE 1 3 Environmental Specification Limits and Ruggedization Levels Card Operating Temperature Storage Temperature Operating Humidity Storage Humidity Sine Vibration note 1 Random Vibration note 4 Mechanical Shock note 5 Air Cooled Level 0 0 C to 50 C inlet 4 cfm air flow note 6 40 C to 85 C 0 to 95 non condensing 0 to 95 non condensing N A N A N A Air Cooled Level 50 20 C to 65 C inlet 4 cfm air ...

Page 28: ...D FEBRUARY 2009 1 13 CONNECTOR PIN ASSIGNMENTS CONNECTOR LOCATIONS The locations of the Pn1 Pn2 Pn3 Pn3 and J1 connectors are shown in Figure 1 8 FIGURE 1 8 Connector Locations Pn1 Pn2 Pn3 Pn4 J1 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com ...

Page 29: ... AD 25 Ground 24 23 AD 24 3 3V 24 25 Ground C BE 3 26 25 IDSEL AD 23 26 27 AD 22 AD 21 28 27 3 3V AD 20 28 29 AD 19 5V 30 29 AD 18 Ground 30 31 V I O AD 17 32 31 AD 16 C BE 2 32 33 FRAME Ground 34 33 Ground PMC RSVD 34 35 Ground IRDY 36 35 TRDY 3 3V 36 37 DEVSEL 5V 38 37 Ground STOP 38 39 Ground LOCK 40 39 PERR Ground 40 41 SDONE SBO 42 41 3 3V SERR 42 43 PAR Ground 44 43 C BE 1 Ground 44 45 V I O...

Page 30: ... 16 17 AD 59 AD 58 18 19 AD 57 GND 20 21 V I O AD 56 22 23 AD 55 AD 54 24 25 Ad 53 GND 26 27 GND AD 52 28 29 AD 51 AD 50 30 31 AD 49 GND 32 33 GND AD 48 34 35 AD 47 AD 46 36 37 AD 45 GND 38 39 V I O AD 44 40 41 AD 43 AD 42 42 43 AD 41 GND 44 45 GND AD 40 46 47 AD 39 AD 38 48 49 AD 37 GND 50 51 GND AD 36 52 53 AD35 AD34 54 55 AD33 GND 56 57 V I O AD32 58 59 PCI RSVD PCI RSVD 60 61 PCI RSVD GND 62 6...

Page 31: ... IRDY TRDY 14 15 5 V SERR 16 17 IDSEL PERR 18 19 STOP TERMDIS 20 21 PAR FRAME 22 23 CLOCKDIS CBE3 24 25 CBE2 CBE0 26 27 CBE1 ARBDIS 28 29 AD0 AD1 30 31 AD2 AD3 32 33 AD4 AD5 34 35 GND AD7 36 37 AD6 AD9 38 39 AD8 AD11 40 41 AD10 AD13 42 43 AD12 GND 44 45 AD14 AD15 46 47 AD16 AD17 48 49 AD18 AD19 50 51 GND AD21 52 53 AD20 AD23 54 55 AD22 AD25 56 57 AD24 AD27 58 59 AD26 GND 60 61 AD28 AD29 62 63 AD30...

Page 32: ...n a SVME DMV 179 Table 1 8 describes the P0 connector of an SVME DMV 179 with a PMC 605 mounted in the PMC1 interface The shaded boxes represent PCI signals provided by the PMC 605 when plugged into the System Slot on the PCI P0 backplane TABLE 1 7 J1 Test JTAG Port Pin Assignments Pin Signal 1 TCK Xilinx Bridge 2 TDI Xilinx 3 TMS Xilinx Bridge 4 TDO Xilinx connects to TDI of Bridge 5 5 V 6 RST Br...

Page 33: ...IDSEL PERR STOP TERMDIS 8 PAR FRAME CLOCKDIS CBE3 CBE2 9 PIO 7 PIO 5 PIO 3 PIO 1 PIO 0 10 PIO 8 PIO 6 PIO 4 PIO 2 Reserved 11 JTAG_TCK JTAG_TDI JTAG_TRST JTAG_TDO Reserved 12 CBE0 CBE1 ARBDIS AD0 AD1 13 AD2 AD3 AD4 AD5 GND 14 AD7 AD6 AD9 AD8 AD11 15 AD10 AD13 AD12 GND AD14 16 AD15 AD16 AD17 AD18 AD19 17 GND AD21 AD20 AD23 AD22 18 AD25 AD24 AD27 AD26 GND 19 AD28 AD29 AD30 AD31 PIO 11 Note To suppor...

Page 34: ... demand The SVME DMV 210 is used in conjunction with the PMC 605 to expand the PCI bus of a processor card a Single Board Computer or SBC through the P0 connector Two SVME DMV 210 cards can be supported by a single SBC expanding the available PMC support to a total of five modules FIGURE 2 1 Sample Application of SVME DMV 210 Carrier Card VMEbus PCI P0 Bus Single Board Computer PMC 605 Custom PMC ...

Page 35: ...ts The SVME DMV 210 requires a 5V 0 25V input power supply from the backplane An on board regulator provides 3 3V capable of providing up to 12 W or 3 5 A The maximum current used by the SVME DMV 210 not including that used by PMC modules is 1000 mA The 12 V and 12 V power supplies from the VMEbus are routed to the PMC modules Ruggedization Levels The SVME DMV 210 is available in air cooled rugged...

Page 36: ...V device that is 5 V tolerant Both the PCI P0 bus and the PMC bus can use either 3 3 V or 5 V independently of each other The SVME DMV 210 incorporates electronic bus switches that permit either 3 3V or a 5V PMC modules to be added with no need to change the configuration 3 3V or 5V PMC modules can be installed in either PMC module site on the SVME DMV 210 in any combination PCI SYSTEM RESET RST T...

Page 37: ... signals are tied to the appropriate logic level on the SVME DMV 210 the Busmode1 signal from each PMC site is connected to the on board CPLD the Busmode2 signal is connected to 3 3V the Busmode3 and Busmode4 signals are connected to Ground The presence of a PMC module is indicated by the assertion of the Busmode1 signal of the corresponding PMC site Artisan Scientific Quality Instrumentation Guar...

Page 38: ...Physical Layout DIMENSIONS The SVME DMV 210 is built on a standard VMEbus 6U Printed Wiring Board PWB and is VITA 20 compliant MATING CONNECTORS The connectors Pn1 Pn2 Pn3 and Pn4 are compliant with IEEE P1386 1 Draft 2 2 April 22 2000 The P1 P2 and P0 connectors conform to the ANSI VITA 1 1994 Draft 1 11 10 April 1995 VME64bus Specification P1 P2 P0 PMC Site 1 PMC Site 2 2 1 4 3 2 1 4 3 Artisan S...

Page 39: ...ating Humidity Storage Humidity Sine Vibration note 1 Random Vibration note 4 Mechanical Shock note 5 Air Cooled Level 0 0 C to 50 C inlet 4 cfm air flow note 6 40 C to 85 C 0 to 95 non condensing 0 to 95 non condensing N A N A N A Air Cooled Level 50 20 C to 65 C inlet 4 cfm air flow note 6 40 C to 85 C 0 to 100 non condensing 0 to 100 non condensing N A 0 02 g2 Hz 20 2000 Hz 30 g peak half sine ...

Page 40: ... 30 AD 29 20 21 AD 28 AD 27 22 21 GND AD 26 22 23 AD 25 GND 24 23 AD 24 3 3V 24 25 GND C BE 3 26 25 PMC1_IDSEL AD 23 26 27 AD 22 AD 21 28 27 3 3V AD 20 28 29 AD 19 5V 30 29 AD 18 GND 30 31 VIO AD 17 32 31 AD 16 C BE 2 32 33 PMC1_FRAME GND 34 33 GND PMC1_PMCR3 34 35 GND PMC1_IRDY 36 35 PMC1_TRDY 3 3V 36 37 PMC1_DEVSEL 5V 38 37 GND PMC1_STOP 38 39 GND PMC1_LOCK 40 39 PMC1_PERR GND 40 41 PMC1_SDONE P...

Page 41: ..._IO 23 PMC1_IO 24 24 25 AD 53 GND 26 25 PMC1_IO 25 PMC1_IO 26 26 27 GND AD 52 28 27 PMC1_IO 27 PMC1_IO 28 28 29 AD 51 AD 50 30 29 PMC1_IO 29 PMC1_IO 30 30 31 AD 49 GND 32 31 PMC1_IO 31 PMC1_IO 32 32 33 GND AD 48 34 33 PMC1_IO 33 PMC1_IO 34 34 35 AD 47 AD 46 36 35 PMC1_IO 35 PMC1_IO 36 36 37 AD 45 GND 38 37 PMC1_IO 37 PMC1_IO 38 38 39 VIO AD 44 40 39 PMC1_IO 39 PMC1_IO 40 40 41 AD 43 AD 42 42 41 PM...

Page 42: ...21 AD 28 AD 27 22 21 GND AD 26 22 23 AD 25 GND 24 23 AD 24 3 3V 24 25 GND C BE 3 26 25 PMC2_IDSEL AD 23 26 27 AD 22 AD 21 28 27 3 3V AD 20 28 29 AD 19 5V 30 29 AD 18 GND 30 31 VIO AD 17 32 31 AD 16 C BE 2 32 33 PMC2_FRAME GND 34 33 GND PMC2_PMCR3 34 35 GND PMC2_IRDY 36 35 PMC2_TRDY 3 3V 36 37 PMC2_DEVSEL 5V 38 37 GND PMC2_STOP 38 39 GND PMC2_LOCK 40 39 PMC2_PERR GND 40 41 PMC2_SDONE PMC2_SBO 42 41...

Page 43: ...2_IO 23 PMC2_IO 24 24 25 AD 53 GND 26 25 PMC2_IO 25 PMC2_IO 26 26 27 GND AD 52 28 27 PMC2_IO 27 PMC2_IO 28 28 29 AD 51 AD 50 30 29 PMC2_IO 29 PMC2_IO 30 30 31 AD 49 GND 32 31 PMC2_IO 31 PMC2_IO 32 32 33 GND AD 48 34 33 PMC2_IO 33 PMC2_IO 34 34 35 AD 47 AD 46 36 35 PMC2_IO 35 PMC2_IO 36 36 37 AD 45 GND 38 37 PMC2_IO 37 PMC2_IO 38 38 39 VIO AD 44 40 39 PMC2_IO 39 PMC2_IO 40 40 41 AD 43 AD 42 42 41 P...

Page 44: ...1 P0_AD 30 P0_AD 29 P0_AD 28 GND Caution The signals assigned to P0 A4 and P0 C4 in Table 2 6 have been swapped in this edition of the manual to accurately reflect the current version of the SVME DMV 210 hardware This change was introduced via ECO 500000000673 Tip Table 2 6 shows generic signal names e g PMC1_IO 11 for the PMC module that may or may not be installed in PMC Site 1 on the SVME DMV 2...

Page 45: ... 13 P1A_NC11 P1B_NC5 P1C_NC12 P1D_NC11 P1Z_NC7 14 P1A_NC12 P1B_NC6 P1C_NC13 P1D_NC12 GND 15 GND P1B_NC7 P1C_NC14 P1D_NC13 P1Z_NC8 16 P1A_NC13 P1B_NC8 P1C_NC15 P1D_NC14 GND 17 GND P1B_NC9 P1C_NC16 P1D_NC15 P1Z_NC9 18 P1A_NC14 P1B_NC10 P1C_NC17 P1D_NC16 GND 19 GND P1B_NC11 P1C_NC18 P1D_NC17 P1Z_NC10 20 P1A_NC15 GND P1C_NC19 P1D_NC18 GND 21 IACK P1B_NC12 P1C_NC20 P1D_NC19 P1Z_NC11 22 IACK P1B_NC13 P1...

Page 46: ... GND 13 PMC2_IO 26 5V PMC2_IO 25 PMC1_IO 38 PMC1_IO 37 14 PMC2_IO 28 NC PMC2_IO 27 PMC1_IO 39 GND 15 PMC2_IO 30 NC PMC2_IO 29 PMC1_IO 41 PMC1_IO 40 16 PMC2_IO 32 NC PMC2_IO 31 PMC1_IO 42 GND 17 PMC2_IO 34 NC PMC2_IO 33 PMC1_IO 44 PMC1_IO 43 18 PMC2_IO 36 NC PMC2_IO 35 PMC1_IO 45 GND 19 PMC2_IO 38 NC PMC2_IO 37 PMC1_IO 47 PMC1_IO 46 20 PMC2_IO 40 NC PMC2_IO 39 PMC1_IO 48 GND 21 PMC2_IO 42 NC PMC2_I...

Page 47: ...tion and included it on the Technical Documentation CD ROM for the OUTREACH PCI PMC Expansion System It allows you to generate the pin assignments table specific to your product configuration by selecting from a list of standard CWCEC PMC modules Alternatively you can load pinout information specific to a third party PMC module or one of your own design and generate the SVME DMV 210 VME P2 pin ass...

Page 48: ...mbers BPL 605 002 and BPL 605 003 The slots are labelled from left to right System Slot 0 Peripheral Slot 1 and Peripheral Slot 2 FIGURE 3 1 PCI P0 Development Backplane Slot Locations 3 Slot Version Pin A1 J1 System Slot 0 J2 Peripheral Slot 1 J3 Peripheral Slot 2 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com ...

Page 49: ...disabled ARBIS signal connected to Vcc Caution The additional configurations included here are for reference purposes only Adjusting the jumper configuration of your PCI P0 development backplane may cause your PMC 605 modules to malfunction Note Some jumpers on the BPL 605 002 and BPL 605 003 are reserved for future use In particular on the BPL 605 002 jumpers E 10 through E 15 are reserved while ...

Page 50: ...ot 0 Connect E1 E2 Slot 1 Connect E23 E24 Additional Possible Configurations Set 605 in Peripheral Slot 1 as Arbiter Slot 0 Connect E1 E2 Slot 1 Connect E14 E15 Slot 2 Connect E34 E35 Set 605 in Peripheral Slot 2 as Arbiter Slot 0 Connect E1 E2 Slot 1 Connect E13 E14 Slot 2 Connect E35 E36 Slot 0 Slot 1 Slot 2 J1 A1 Rear View 3 Slot Backplane BPL 605 003 E1 E2 E3 E13 E14 E15 E34 E35 E36 Slot 0 Slo...

Page 51: ... Slot 1 Connect E19 E20 Recommended Setting 605 in Slot 0 providing clock source Slot 0 Connect E5 E6 Slot 1 Connect E16 E17 Slot 2 Connect E31 E32 Additional Possible Configurations 605 in Slot 1 providing clock source Slot 0 Connect E4 E5 Slot 1 Connect E20 E21 Additional Possible Configurations 605 in Slot 1 providing clock source Slot 0 Connect E4 E5 Slot 1 Connect E17 E18 Slot 2 Connect E31 E...

Page 52: ...lot Termination Jumper Settings 2 Slot Backplane 3 Slot Backplane Recommended Setting 605 in System Slot 0 terminating bus signals Slot 0 Connect E8 E9 Slot 1 Connect E16 E17 Recommended Setting 605 in System Slot 0 terminating bus signals Slot 0 Connect E8 E9 Slot 1 Connect E19 E20 Slot 2 Connect E28 E29 Additional Possible Configurations 605 in Slot 1 terminating bus signals Slot 0 Connect E7 E8...

Page 53: ...unted on the opposite side of the above circuit cards plug into the corresponding P0 connectors on the rear of the VME backplane Slot 0 Slot 1 Slot 2 J1 A1 Rear View 3 Slot Backplane BPL 605 003 E7 E8 E9 E19 E20 E21 E28 E29 E30 Slot 0 Slot 1 J1 A1 Rear View 2 Slot Backplane BPL 605 002 E7 E8 E9 E16 E17 E18 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific c...

Page 54: ...C5 CLK1 The peripheral card takes its clock from its D4 pin System Slot pin C5 connects to the peripheral slot s D4 pin Reset The Reset line is common on pin E4 and should only be driven from Slot 0 Interrupts The interrupt line INTA is common on pin E5 5 V Rail The 5 V rail pin A6 that goes to each P0 connector is isolated for each slot Ground The GND signal is common across all slots Request Lin...

Page 55: ...rd signal 4 RST CLK0 REQ0 GND GNT0 5 INTA GND CLK1 REQ1 DESEL 6 GNT1 SERARB_1 IRDY TRDY 5 V 7 SERR IDSEL_1 PERR STOP TERMDIS_1 8 PAR FRAME CLOCKDIS_1 CBE3 CBE2 9 basecard signal basecard signal basecard signal basecard signal basecard signal 10 basecard signal basecard signal basecard signal basecard signal basecard signal 11 basecard signal basecard signal basecard signal basecard signal basecard...

Page 56: ...GND GNT0 REQ0 5 INTA GND CLK1 not connected REQ1 not connected DESEL 6 GNT1 not connected SERARB_2 IRDY TRDY 5 V 7 SERR IDSEL_2 PERR STOP TERMDIS_2 8 PAR FRAME CLOCKDIS_2 CBE3 CBE2 9 basecard signal basecard signal basecard signal basecard signal basecard signal 10 basecard signal basecard signal basecard signal basecard signal basecard signal 11 basecard signal basecard signal basecard signal bas...

Page 57: ...eripheral Slot 2 pin D4 Reset The Reset line is common on pin E4 and should only be driven from Slot 0 Interrupts The interrupt line INTA is common on pin E5 5 V Rail The 5 V rail pin A6 that goes to each P0 connector is isolated for each slot Ground The GND signal is common across all slots Request Line The REQ0 line on the System Slot pin C4 is driven by the REQ0 line on Peripheral Slot 1 pin A4...

Page 58: ...LK0 REQ0 GND GNT0 5 INTA GND CLK1 REQ1 DESEL 6 GNT1 SERARB_1 IRDY TRDY 5 V 7 SERR IDSEL_1 PERR STOP TERMDIS_1 8 PAR FRAME CLOCKDIS_1 CBE3 CBE2 9 basecard signal basecard signal basecard signal basecard signal basecard signal 10 basecard signal basecard signal basecard signal basecard signal basecard signal 11 basecard signal basecard signal basecard signal basecard signal basecard signal 12 CBE0 C...

Page 59: ...0 GND GNT0 REQ0 5 INTA GND CLK1 not connected REQ1 not connected DESEL 6 GNT1 not connected SERARB_2 IRDY TRDY 5 V 7 SERR IDSEL_2 PERR STOP TERMDIS_2 8 PAR FRAME CLOCKDIS_2 CBE3 CBE2 9 basecard signal basecard signal basecard signal basecard signal basecard signal 10 basecard signal basecard signal basecard signal basecard signal basecard signal 11 basecard signal basecard signal basecard signal b...

Page 60: ...0 REQ0 5 INTA GND CLK1 not connected REQ1 not connected DESEL 6 GNT1 not connected SERARB_3 IRDY TRDY 5 V 7 SERR IDSEL_3 PERR STOP TERMDIS_3 8 PAR FRAME CLOCKDIS_3 CBE3 CBE2 9 basecard signal basecard signal basecard signal basecard signal basecard signal 10 basecard signal basecard signal basecard signal basecard signal basecard signal 11 basecard signal basecard signal basecard signal basecard s...

Page 61: ...CI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING 3 14 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com ...

Page 62: ...pagate between the two PCI domains SVME DMV 210 TRANSPARENT PCI PCI BRIDGING The SVME DMV 210 uses the Intel 21154 PCI PCI Bridge device The 21154 is a transparent PCI PCI bridge and therefore the internal PCI bus of the SVME DMV 210 is a transparent extension to the PCI P0 bus The 21154 does allow configuration transactions to cross the bridge In a system with more than one SBC and one or more SV...

Page 63: ...21554 PCI bridge The PCI P0 bus connects to the P0 backplane and to the primary side of the 21554 As shown in Figure 4 1 Upstream refers to the direction toward the PCI P0 bus and Downstream refers to direction toward the local PCI bus FIGURE 4 1 Primary and Secondary PCI Buses Primary I F Secondary I F PMC 605 PCI P0 Bus Local PCI Bus Upstream Downstream Artisan Scientific Quality Instrumentation...

Page 64: ...a serial EEPROM read in order to perform a configuration register preload Among other things the preload is used to select the size and type of downstream and upstream address windows by preloading the address setup configuration registers VMEbus PCI P0 Bus Single Board Computer Single Board Computer SVME DMV 210 Carrier Card PMC 605 PMC 605 Custom PMC I O Card Custom PMC I O Card Note The serial ...

Page 65: ...arning Do not change this value B 0x00 Primary Min GNT Max LAT C 0x00 D 0x00 Secondary Class code E 0x80 F 0x06 10 0x00 Secondary Min GNT Max LAT 11 0x00 12 0x00 Downstream Mem0 CSRs only set a 4 Kbyte window size for CSRs 13 0xF0 14 0xFF 15 0xFF 16 0x00 Downstream Mem1 or I O set 1 Mbyte memory size window 17 0x00 18 0xF0 19 0xFF 1A 0x00 Downstream Mem 2 not used 1B 0x00 1C 0x00 1D 0x00 1E 0x00 D...

Page 66: ...p Control 1 33 0x00 LUT disable I20 disable 34 0x00 Arbiter Control not used 35 0x00 36 0x00 System error disable 37 0x00 38 0x00 Power management 39 0x00 3A 0x00 3B 0x00 3C 0x00 3D 0x00 3E 0x00 3F 0x00 40 0x00 41 0x00 42 0x00 TABLE 4 1 Serial EEPROM Factory Default Values Offset Data Description Cross Reference These default values listed above can be changed using the PMC 605 service Pmc605_writ...

Page 67: ...x6320 0x00 0x80000000 0 0x00000000 Memory 1 0x01000000 Memory 2 0x1C000000 Memory 3 0xFF000000 Memory 4 0xF0000000 Memory Universe 0x10E3 0x0000 0x00 0x80003000 0 0xD0001000 0x00001000 Memory 1 0xE0001000 0x00001000 I O SYM53C885ET 0x1000 0x0701 0x80 0x80004100 0 0xE0000000 0x00000100 I O 1 0xD0000000 0x00000100 Memory SYM53C885SC 0x1000 0x000D 0x80 0x80004000 0 0xE0000100 0x00000100 I O 1 0xD0000...

Page 68: ... using the CSS function Find_device For example pciDeviceStruct dev Find_device I21554_DEVICE_ID INTEL_VENDOR_ID 0 dev Offset 0 uint32 dev memBaseAddr 0 Secondary CSR Memory BAR Offset 1 uint32 dev memBaseAddr 1 Upstream Memory 1 BAR Offset 2 uint32 dev ioBaseAddr 0 Secondary CSR I O BAR Offset 3 uint32 dev ioBaseAddr 1 Upstream I O BAR Alternatively the Secondary PCI Configuration register defaul...

Page 69: ...terupt pin 0x01 interupt line 0x00 40000000 PRIMARY BAR CONFIGURATION Once the Secondary BARs are configured then the Primary BARs of the PMC 605 must be configured This can be achieved by any device with access to the PCI P0 bus configuration space In this example the host SBC in slot 1 will configure the primary BARs of its own PMC 605 via the PMC 605 s Secondary interface configuration space an...

Page 70: ...mary Configuration Space offset Set Base address for Slave SBC s RAM using Downstream I O or Memory 1 BAR Pmc605_pciP0ConfigWrite busNo deviceNo functionNo 0x18 0x100000 sizeof uint32 Set Base address for Slaves s PMC605 CSRs in PCI P0 memory space Pmc605_pciP0ConfigWrite busNo deviceNo functionNo 0x10 0x301000 sizeof uint32 Set Base address for Masters s PMC605 CSRs in PCI P0 I O space Pmc605_pci...

Page 71: ...ry 1 Translated Base Register to translate addresses decoded by the Secondary Upstream I O or Mem 1 BAR to PCI P0 I O base address 0x0 PciConfigWrite busNo deviceNo functionNo 0xA4 0x0 sizeof uint32 Set the Upstream Memory 1 Translated Base Register to translate addresses decoded by the Secondary Upstream Memory 1 BAR to PCI P0 memory base address 0x0 PciConfigWrite busNo deviceNo functionNo 0xA8 ...

Page 72: ...ase uint32 uint32 dev ioBaseAddr 1 0x100 slaveCsrIoBase regData offset 0 Start of PCI memory Offset 0 0x1000 0x0000 0000 PMC605 CSRs Offset 1 0x400000 PCI P0 Memory Space Start of PCI I O offset 2 0x100 offset 3 0x400 PCI P0 I O Space PMC605 CSRs offset 1 offset 2 offset 3 Master SBC Address map 0x0000 0000 PCI P0 Memory map 0x0010 0000 0x0020 0000 0x0030 0000 0x0030 1000 0x0030 2000 Master SBC RA...

Page 73: ...ermine the function number of the device and register offset within that function for the selected slot Refer to the PCI specification 2 2 for an explanation of Type 0 and 1 configuration cycles ADDRESSING EXAMPLE Suppose you wish to read the Primary CSR and Downstream Memory 0 Base Address Register BAR on the PMC 605 in slot 2 Using the PMC 605 service Pmc605_pciPoConfigRead you would construct t...

Page 74: ...f a PCI to PCI bridge other than a PMC 605 the bus number must be greater than zero In this instance the values are passed straight through to the PCI P0 bus as follows FIGURE 4 7 Type 1 Configuration Cycle Example 0 0 0 0 Reserved Bus No 0 Dev No 1 Func No 0 Reg No 0x10 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 2 7 8 10 11 15 16 23 24 31 31 11 10 0 PCI P0 address 1 0 0 1 Res...

Page 75: ...CI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING 4 14 809524 REVISION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com ...

Page 76: ...e or more Single Board Computers each equipped with a PMC 605 module one or more SVME DMV 210 Carrier Cards each equipped with one or two PMC mod ules one CWCEC PCI P0 development backplane identified as either BPL 605 002 or BPL 605 003 one standard VME development chassis FIGURE A 1 Outreach PCI PMC Expansion System Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan ...

Page 77: ...ser definable jumper settings Configuration is done via the PCI P0 development backplane Caution Remove the cards from their protective package only at a grounded workstation while wearing an approved grounding wrist strap Avoid touching any metal contacts on the cards static discharge can damage integrated circuits Cross Reference The PCI P0 development backplane identified as either BPL 605 002 ...

Page 78: ...ra care when aligning and inserting your SBCs into your chassis to ensure that a secure mechanical and electrical connection is made between the cards and the backplane mating connectors PMC 605 Single Board Computer P1 P2 P0 Cross Reference In most cases the PMC 605 will have already been mounted on the basecard at the factory to ensure proper mechanical and thermal mating connections If necessar...

Page 79: ...her cards equipped with PMC 605 cards ATTACH THE PCI P0 DEVELOPMENT BACKPLANE Attach the PCI P0 development backplane either the BPL 605 002 or the BPL 605 003 to the back of the VME backplane Depending on your system your PCI P0 development backplane may support 2 or 3 slots FIGURE A 3 PCI P0 Backplane Installation Caution Be careful not to bend any pins when attaching the PCI P0 development back...

Page 80: ...will inform the GPM that I O data is being received from the serial data port The GPM will then display a sign on message similar to the following SVME 179 PowerPC 750 General Purpose Monitor Version 8 0 c CWCEC Systems Inc Type for help 40000000 The last line is the initial prompt which shows the VMEbus base address of the card In this example the base address is 4000 0000h Type at the prompt to ...

Page 81: ...9 INSTALL BSP Cross Reference Once the hardware is correctly configured and installed in the chassis the next step is to install the host card s board support package software See the BSP Software User s Manual for more information Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com ...

Page 82: ... Arbiter jumper settings 3 3 bus arbitration 1 3 bus clock source 1 6 C card insertion force A 3 cautionary note ARBDIS signal 1 5 CLKDIS signal 1 6 CLKDIS signal 1 6 clock speed 1 3 clock source configurations 1 7 component locations PMC 605 1 11 SVME DMV 210 2 5 configuration register preload 4 3 connector locations PMC 605 1 11 1 13 SVME DMV 210 2 5 D device ID 1 10 diagnostics A 5 dimensions 1...

Page 83: ...igWrite 4 9 Pmc605_writeSeeprom service 4 3 4 5 Pn1 pin assignments 1 14 Pn2 pin assignments 1 14 Pn3 pin assignments 1 15 Pn4 pin assignments 1 16 power requirements PMC 605 1 12 preload enable bit 4 3 Primary PCI bus 1 4 R random vibration 1 12 2 6 reset 1 9 Reset signal 1 9 ruggedization levels PMC 605 1 12 SVME DMV 210 2 2 S sample application 1 1 Secondary PCI bus 1 4 serial EEPROM 1 3 1 10 c...

Page 84: ...809524 VERSION D FEBRUARY 2009 I 3 V VME P0 Connector pin assignments 2 11 VME P1 Connector pin assignments 2 12 VME P2 Connector pin assignments 2 13 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com ...

Page 85: ...PCI PMC EXPANSION SYSTEM USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING I 4 809524 VERSION D FEBRUARY 2009 Artisan Scientific Quality Instrumentation Guaranteed 888 88 SOURCE www artisan scientific com ...

Page 86: ...quipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentation Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate representative or authorized distributor for any manufacturer listed herein We re here to make your life easier How...

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