Curtiss-Wright FHF5-PC4MWB04-00 Hardware Reference Manual Download Page 49

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APPENDIX B - REGISTER SET

TABLE OF CONTENTS

6.1 Overview ................................................................................................................... 6-1

6.2 Accessible resources.................................................................................................. 6-1

6.3 PCI Configuration registers ....................................................................................... 6-1

6.4 Runtime Register set ................................................................................................. 6-1

6.4.1 Bit Definitions .......................................................................................... 6-1

6.4.2 Interrupt CSR (INT_CSR) – Offset 0x00 ................................................. 6-3

6.4.3 Board CSR (BRD_CSR) – Offset 0x04 ................................................... 6-4

6.4.4 Link Control (LINK_CTL) – Offset 0x08 ............................................... 6-5

6.4.5 Link Status (LINK_STAT) – Offset 0x0C ............................................... 6-8

6.4.6 FPDP Flags (FPDP_FLGS) – Offset 0x10 ............................................... 6-9

6.4.7 Receive FIFO Threshold – Offset 0x14 ................................................ 6-10

6.4.8 Laser Transmitter Control – Offset 0x18 ............................................... 6-10

6.4.9 Transaction Channel 0 (Send Channel) .................................................. 6-11

6.4.10 Transaction Channel 1 (Receive Channel) ........................................... 6-14

Summary of Contents for FHF5-PC4MWB04-00

Page 1: ... SL100 SL240 Hardware Reference for PCI and PMC Cards Document No DDOC0076 000 AN F T MR S2PCIPMC A 0 AN ...

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Page 3: ...nt are protected by one or both of the following U S patents 6 751 699 and 5 982 634 is a registered trademark of Curtiss Wright Controls Inc is a registered trademark of Curtiss Wright Controls Inc is a registered trademark of Curtiss Wright Controls Inc Date Change Summery Pg Rev Number 07 05 17 Addition of SL100 5volt Rugged card 33MHz PCN 1202 2 3 4 5 12 5 2 8 1 AM 10 02 17 Rugged Level 2 SL10...

Page 4: ...th other radio and communication devices The user may be in violation of FCC regulations if this device is used in other than the intended market environments CE As a component part of another system this information technology product has no direct function and is therefore not subject to applicable European Union directives for Information Technology equipment ...

Page 5: ...2 8 2 5 2 Point to point 2 8 2 5 3 Chained 2 9 2 5 4 Single Master Ring 2 10 2 5 5 Multiple Master Ring 2 11 2 6 Status LEDs 2 12 2 6 1 LED Description for SL100 and SL240 33MHz Cards 2 12 2 6 2 LED Description for SL240 66MHz Cards 2 13 3 INSTALLATION 3 1 3 1 Overview 3 1 3 2 Unpack the Cards 3 1 3 3 Inspect the Cards 3 1 3 4 Configure the SL240 Card 3 1 3 4 1 Installing SFP Modules 3 1 3 5 Insta...

Page 6: ...2 Accessible resources 6 1 6 3 PCI Configuration registers 6 1 6 4 Runtime Register set 6 1 6 4 1 Bit Definitions 6 1 6 4 2 Interrupt CSR INT_CSR Offset 0x00 6 3 6 4 3 Board CSR BRD_CSR Offset 0x04 6 4 6 4 4 Link Control LINK_CTL Offset 0x08 6 5 6 4 5 Link Status LINK_STAT Offset 0x0C 6 8 6 4 6 FPDP Flags FPDP_FLGS Offset 0x10 6 9 6 4 7 Receive FIFO Threshold Offset 0x14 6 10 6 4 8 Laser Transmitt...

Page 7: ...gged Card 2 3 Figure 2 6 SL240 PMC 33 MHz Card 2 4 Figure 2 7 SFP Transceiver Module 2 5 Figure 2 8 Typical Applications of FibreXtreme SL240 in Advanced DSP Systems 2 7 Figure 2 9 FibreXtreme SL240 Extending FPDP 2 8 Figure 2 10 Point to Point Topology 2 9 Figure 2 11 Chained Topology 2 9 Figure 2 12 Single Master Ring 2 10 Figure 2 13 Multiple Master Ring 2 11 Figure 2 14 SL100 5 Volt PMC and SL...

Page 9: ...the following information An introduction to FibreXtreme SL240 Applications and topologies for SL240 boards Instructions for installing and configuring the card An operational overview of the product General card specifications Register set information Programming information Summary of the protocol used by the SL240 boards Ordering information for all products mentioned in this manual A brief int...

Page 10: ...ser Diode and LED Sources Draft Standard for a Common Mezzanine Card Family CMC IEEE P1386 Draft 2 0 April 4 1995 Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC IEEE P1386 1 2 0 April 4 1995 Fibre Channel Association Product Information Bulletin Revision December 9 1994 Fibre Channel Physical and Signaling Interface FC PH Revision 4 3 June 1 1994 Produced by the ANSI ...

Page 11: ... procedures Improve the quality of our operations to meet the needs of our customers suppliers and other stakeholders Provide our employees with the tools and overall work environment to fulfill maintain and improve product and service quality Ensure our customer and other stakeholders that only the highest quality product or service will be delivered The British Standards Institution BSI the worl...

Page 12: ...his document comprehensive you may have specific problems or issues this document does not satisfactorily cover Our goal is to offer a combination of products and services that provide complete easy to use solutions for your application If you have any technical or non technical questions or comments contact us Hours of operation are from 8 00 a m to 5 00 p m Eastern Standard Daylight Time Phone 9...

Page 13: ...lution with standard FPDP connectors and a rehostable Common Mezzanine Card CMC The PCI and PMC versions provide this link via the PCI bus The PCI bus is used in most standard PCs and the PMC format is used in most popular single board computers The FPDP versions of the card provide this interface through a simple unidirectional parallel port This port can be connected to existing FPDP equipment o...

Page 16: ...built in data synchronization with very little reduction in throughput Integrated interrupt controller to report link failure transaction completion or buffer space request Status LED that reports link stability Loop operation with out of band arbitration or point to point operation Provides a register set designed for easy programming and status retrieval Small Form Factor SFF media option availa...

Page 17: ...the SL240 These media options include a long reach wavelength laser 1550 nm a long wavelength laser 1300 nm and HSSDC2 copper All cards use a Duplex LC style connector or HSSDC2 receptacle available from most major cable manufacturers Contact Curtiss Wright Controls for the latest SFP options available Figure 2 7 SFP Transceiver Module Long wavelength laser interconnections are recommended for dis...

Page 18: ...Form Factor Pluggable XFP modules FW1600 48 port IEEE 1394b Firewire copper media ET1000 48 port auto negotiation 10 100 or 1000 Mbps Ethernet with RJ 45 connectors Contact Curtiss Wright Controls for a complete list of available port cards Port cards and pluggable transceivers may be mixed in one system Supports Loop Point to Point One to Many communication links Supports multiple physical media ...

Page 19: ...Storage Radar IR Sonar Acoustic Photon Video Etc 105 MBps 100 MBps 105 MBps 105 MBps SL100 SL240 Fibre Channel FULL FC 4 FIBRE CHANNEL IS GOOD FOR STORAGE WORKSTATION CONNECTIONS BUT TOO MUCH OVERHEAD LATENCY FOR MOST SENSOR CONNECTIONS 100 MBps 100 MBps 100 MBps Figure 2 8 Typical Applications of FibreXtreme SL240 in Advanced DSP Systems 2 4 3 Extending FPDP The maximum allowable length for FPDP ...

Page 20: ...on available in this mode is whether flow control is used or not If flow control is used the transmitter on each end will not transmit when the remote receiver is telling it to back off or the receive fiber is missing In this mode the maximum amount of data that can be transferred is 247 MB s per direction in this case both cards are receiving and transmitting 247 MB s at the same time The maximum...

Page 21: ...ong string of receivers No flow control is available in this topology and the distance between the nodes is limited only by the transceivers used 10 km typical 26 km maximum This topology is good for broadcasting data to multiple destinations where late data is of no use such as video transmission applications RX TX RX TX RX TX RX TX SL240 Card SL240 Card SL240 Card SL240 Card Figure 2 11 Chained ...

Page 22: ...e is the LinkXchange GLX4000 Physical Layer Switch available from Curtiss Wright Controls Inc Software controls mastership switching of the ring There are rules associated with master switching listed in the Programming Interface section The flow control used in this case is similar to a multi drop FPDP bus where any receiver can back the transmitter off This is the typical configuration for recor...

Page 23: ...he previous master and sends data to the next master Flow control is not allowed in this topology for rings above two nodes and the data cannot be passed through masters unless control guarantees that there is at least one source only node on the ring and that no two masters will transmit at the same time Single master rings should temporarily become multiple master rings when switching loop maste...

Page 24: ...k Select LS This LED is reserved for future use The on off condition of this LED is of no consequence Link Up LU The Link Up LED turns on when receiving a valid SL240 signal Signal Detect RX The Signal Detect LEDs indicate a signal is being received by the transceiver This LED gives no indication of the validity of the signal only that a signal is present Laser Enable TX The Laser Enable LEDs indi...

Page 25: ... turns on when receiving a valid SL240 signal Signal Detect R1 The Signal Detect LEDs indicate a signal is being received by the transceiver This LED gives no indication of the validity of the signal only that a signal is present Laser Enable T1 The Laser Enable LEDs indicate the transceiver is turned on Reserved LEDs This LED is reserved for future use The on off condition of this LED is of no co...

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Page 27: ...ent that you should need to return your SL240 card please keep the original shipping materials for this purpose Any optional equipment is shipped in separate cartons 3 3 Inspect the Cards The SL240 card consists of a single card with a built in link interface If the card was damaged in shipping notify Curtiss Wright Controls Inc or your supplier immediately 3 4 Configure the SL240 Card 3 4 1 Insta...

Page 28: ...module This is usually a button or tab on the bottom side of the module that moves toward the rear of the card The module will pop out slightly as the latch releases Pull the module out of the receptacle cage The SL240 cards are shipped with a Dust EMI plug for each SFP transceiver receptacle Install these in empty receptacles to prevent contamination of internal components and to optimize EMI per...

Page 29: ...to the carrier front panel cutout until it butts up against the mating connector as shown in Figure 3 2 steps 1 and 2 Then firmly push the connectors together Install the four mounting screws through the host PCB to fasten the SL240 PMC card in place as shown in step 3 Figure 3 2 SL240 PMC Card Installation Step 1 Viewed from Front Step1 Viewed from rear Step 2 Step 3 ...

Page 30: ...s is inserted into the transmitter receiver connector it may not be possible to clean the connector out and could result in damage to the transmitter or receiver lens Hair dirt and dust can interfere with the light signal transmission Use an alcohol based wipe to clean the cable ends For short wavelength laser modules either a 50 µm or 62 5 µm core diameter cable should be used For distances up to...

Page 31: ...scription 1 Ground 5 Transmit 2 Receive 6 Transmit 3 Receive 7 Ground 4 Ground Table 3 2 HSSDC2 Receptacle Pin Assignments for SL240 Pin Number Pin Description 1 Ground 2 Receive 3 Receive 4 Ground 5 Transmit 6 Transmit 7 Ground To insure data integrity take care when selecting the appropriate HSSDC2 cable assembly for the SL240 application Application data rate and the presence of equalization ci...

Page 32: ...tance Please be prepared to supply the following information Machine __________________________________________ OS Name __________________________________________ OS Version __________________________________________ Card Type __________________________________________ Card Serial __________________________________________ Software Part __________________________________________ Software S N _____...

Page 33: ... or take data from the link and pass it to the host bus interface The link protocol involved is kept minimal to reduce the latency and improve throughput while still providing a set of useful features with which to customize your applications The hardware offers many different features for advanced applications while maintaining a simple interface to the most commonly used features NOTE For furthe...

Page 34: ...similar fashion although the maximum frame size does differ for these types of associated Serial FPDP frames All FPDP signals with the exclusion of SYNC are passed around the transmit FIFO and are not synchronized with the data stream For PCI variations of this card the FPDP signals can be written to a register and then transmitted across the link 4 2 3 Loop Operation In the Loop Operation discuss...

Page 35: ...transmitted according to their received link values NRDY received from the link translates to NRDY output from the FPDP receiver FPDP RM or FPDP R port Thus reception of NRDY from the link interface may be used to back off the FPDP transmitter depending of the usage of NRDY used by the respective FPDP transmit master Curtiss Wright Controls SL100 SL240 CMC cards when functioning as a FPDP transmit...

Page 36: ...l continue to send data even when the receiver signals it to stop or when the link is down In almost every application flow control should be enabled Even if the application must sustain maximum link throughput it is better to drop the data at the sending source should the system experience a temporary overload condition In some rare cases flow control is not desirable In these cases very careful ...

Page 37: ... are two DMA stop conditions available to the user stop on link error and stop on SYNC The stop on link error stops the DMA engine from removing data from the receive FIFO when there is a link error such as the link going down The stop on SYNC option allows you to stop data from being received from the receive FIFO when a SYNC without DVALID is received on the output 4 5 5 Receive FIFO Threshold I...

Page 39: ...ged Level 2 5 4 5 2 Ruggedized PMC Environmental Specifications 5 5 5 2 1 Rugged Level 2 5 5 5 3 Media Interface Specifications 5 6 5 3 1 SL100 Fibre Optic Media Interface Specifications 5 6 5 3 2 SL240 Fibre Optic Media Interface Specifications 5 7 5 3 3 HSSDC2 Copper Media Interface 1 0625 Gbps 5 7 5 3 4 HSSDC2 Copper Media Interface 2 5 Gbps 5 7 5 3 5 SL100 Fibre Optic Media with 60 MHz Clock O...

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Page 41: ... is highly system dependent and varies from system to system 5 1 1 33 MHz PCI Specifications Physical Dimensions 174 6 mm x 106 7 mm 6 87 inches x 4 173 inches Weight 0 25 lbs Operating Voltage 4 75 V to 5 25 V Power Dissipation SL100 5 1 W Peak 3 1 W Average SL240 7 4 W Peak 4 3 W Average Electrical Requirements SL100 5 VDC 1 02 Amps Peak 0 62 Amps Average SL240 5 VDC 1 48 Amps Peak 0 86 Amps Ave...

Page 42: ...100 5 1 W Peak 3 1 W Average SL240 7 4 W Peak 4 3W Average Electrical Requirements SL100 5VDC 1 02 Amps Peak 0 62 Amps Average SL240 5VDC 1 48 Amps Peak 0 86 Amps Average Operating Temperature Range 0 to 50 C with 200 LFM air minimum 10 C to 70 C Rugged Level 1 Mean Time Between Failure MTBF SL100 Short wavelength laser 458 781 hours 52 4 years SL240 Short wavelength laser 458 433 hours 52 3 years...

Page 43: ...wavelength laser 783 454 hours 89 4 years SL240 Short wavelength laser 782 438 hours 89 3 years Storage Temperature Range 40 to 85 C 5 1 4 66 MHz PMC Specifications Physical Dimensions 74 0 mm x 149 0 mm 2 913 inches x 5 866 inches Weight 0 25 lbs Operating Voltage 5V 5 Power Dissipation SL100 5 1W Peak 3 1W Average SL240 7 4W Peak 4 3W Average Electrical Requirements SL100 5VDC 1 02 Amps Peak 0 6...

Page 44: ...tion SL100 5 3W Peak at 3 3V SL240 7 2W Peak at 3 3V Electrical Requirements SL100 1 61A Peak 3 3 V SL240 2 18A Peak at 3 3V Operating Temperature Range 40 to 85 C Storage Temperature Range 40 to 85 C Mean Time Between Failures MTBF SL100 Short wavelength laser 362 131 hours 41 3 Years SL240 Short wavelength laser 361 539 hours 41 3 Years The MTBF numbers are based on calculations using MIL HDBK 2...

Page 45: ...o 85 C Humidity Range Operating 0 to 95 noncondensing Storage 0 to 95 noncondensing Altitude Operating 25 000 ft steady rapid decompression to 40 000 ft Storage 25 000 ft Vibration Sine 10 g peak 10 Hz to 2 kHz Random 1 g2 Hz 10 Hz to 2 kHz 6 dB octave 1 kHz to 2 kHz Shock 30 g peak sine wave 11 ms duration Airflow 300 LFM Conformal Coating Acrylic HumiSeal 1B31 Ruggedized cards are coated with Hu...

Page 46: ...nsmit Power 10 to 4 dBm Receive Wavelength 770 to 860 nm Receive Sensitivity 16 to 0 dBm 1300 nm Media 9 m single mode fiber Fibre Channel Formats 100 SM LL I 1 Gbps single mode fiber intermediate distance 100 SM LC L 1 Gbps single mode fiber low cost long distance Maximum Fiber Length 10 km Transmit Wavelength 1285 to 1330 nm Transmit Power 9 to 3 dBm Receive Wavelength 1100 to 1600 nm Receive Se...

Page 47: ...9 to 0 dBm 1550 nm Media 8 3 125 m single mode fiber Maximum Fiber Length 26 km max 10 km min Transmit Wavelength 1500 to 1580 nm Transmit Power 2 to 3 dBm Receive Wavelength 1500 to 1580 nm Receive Sensitivity 30 to 6 dBm 5 3 3 HSSDC2 Copper Media Interface 1 0625 Gbps Maximum Data Rate 1 0625 Gbps Connector HSSDC2 Fibre Channel Cable 150 Ohm shielded Quad Copper Maximum Cable Length 30 meters eq...

Page 49: ...rupt CSR INT_CSR Offset 0x00 6 3 6 4 3 Board CSR BRD_CSR Offset 0x04 6 4 6 4 4 Link Control LINK_CTL Offset 0x08 6 5 6 4 5 Link Status LINK_STAT Offset 0x0C 6 8 6 4 6 FPDP Flags FPDP_FLGS Offset 0x10 6 9 6 4 7 Receive FIFO Threshold Offset 0x14 6 10 6 4 8 Laser Transmitter Control Offset 0x18 6 10 6 4 9 Transaction Channel 0 Send Channel 6 11 6 4 10 Transaction Channel 1 Receive Channel 6 14 ...

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Page 51: ...isters the runtime register set and the FIFO The mechanisms for accessing these are platform specific and therefore outside the scope of this document though the contents are detailed here 6 3 PCI Configuration registers The PCI SL240 card contains a standard PCI configuration space header with the device ID of 0x4640 and the vendor ID of 0x1387 There are also two base addresses initialized for th...

Page 52: ...ess 0 0x28 Reserved Queue Control 0 0x30 Transaction Length 0 Transaction CSR 0 0x38 Reserved Reserved 0x40 Reserved Chain PCI Address 0 0x48 Next Chain Entry 0 Chain Length Flags 0 0x50 Reserved Queue Address 1 0x58 Reserved Queue Control 1 0x60 Transaction Length 1 Transaction CSR 1 0x68 Reserved Reserved 0x70 Reserved Chain PCI Address 1 0x78 Next Chain Entry 1 Chain Length Flags 1 0x80 Reserve...

Page 53: ... 0 5 FPDP Interrupt Active A 1 indicates active a 0 indicates not active Write 1 to clear R WOC 0 6 Threshold Interrupt A 1 indicates active a 0 indicates not active Write 1 to clear R WOC 0 15 to 7 Reserved None 0 16 Enable Transaction Channel 0 Interrupt Set to 1 to enable interrupts set to 0 to disable R W 0 17 Enable Transaction Channel 1 Interrupt Set to 1 to enable interrupts set to 0 to dis...

Page 54: ...ages However the 33 MHz design supports only 5V signaling and the hardware is keyed to only support 5V PCI plots A 1 indicates the SL100 SL240 card uses 3 3 V PCI signaling A 0 indicates the SL100 SL240 card uses 5 V PCI signaling R See desc 15 SL100 SL240 A 1 indicates this is an SL240 board a 0 indicates it is an SL100 R See desc 23 to 16 Extended Revision ID These bits are used to identify inte...

Page 55: ... control from the remote end and continue transmitting when the link is down Set to 0 to stop transmission when the link goes down or the remote end is sending a STOP ordered set back NOTE In almost every application flow control should be enabled Even if the application must sustain maximum link throughput it is better to drop the data at the sending source should the system experience a temporar...

Page 56: ...ode is enabled via the LWRAP bit R W 0 10 EWRAP This signal controls loopback operation of the user interface s data stream A 1 indicates the outgoing data stream is electronically wrapped into the incoming data stream at the serializer deserializer A 0 indicates non wrapped data flow to and from the link interface This is typically used for testing purposes R W 0 11 LWRAP This signal controls the...

Page 57: ...his bit is included for testing and special scenarios and as such should not be used in the majority of applications Resetting the Transmit FIFO or Receive FIFO independently from the SL100 SL240 FPGA logic can cause undesirable effects because each 32 bit Serial FPDP data word occupies two entries in the respective FIFO and the link and host are independently filling and draining these FIFOs Appl...

Page 58: ...own bit R 0 10 Synchronization Error A 1 indicates the card has corrected a synchronization error on the incoming data stream A 0 indicates the card has not corrected a synchronization error on the incoming data stream This bit is cleared through Reset SR in LINK_CTL R 0 11 Checksum Error A 1 indicates the card has detected a checksum error on the incoming data stream A 0 indicates the card has no...

Page 59: ...at a STOP flow control primitive was sent to the remote transmitter This bit is read only and will be dynamically changing R 0 15 FIFO Overflow Indicates that the Remote Transmitter FIFO Overflow bit was set in the received Status End of Frame primitive EOFa or EOFn Fibre Channel ordered sets This indicates that the remote node detected an overflow condition in its transmit FIFO This bit is read o...

Page 60: ...ve FIFO R 0 20 Rearm Threshold Interrupt Write 1 to rearm the threshold register Writing 0 has no effect W 0 21 Data present A 1 indicates data is present on the output A 0 indicates no data is present R 0 29 to 22 Reserved None 0 31 to 30 Interrupt Threshold Selects one of the following levels of the Receive FIFO to interrupt on 00 Interrupt threshold set to Receive FIFO Not Empty 01 Interrupt th...

Page 61: ...a power of 2 Maximum 32 R W 0 23 to 21 Reserved None 0 24 Enable Queue A 1 enables the queue to fetch transaction entries Setting this bit to 0 pauses the transaction queue R W 0 25 Reset Queue Write 1 to set the consumer and producer indices to 0 Writing 0 has no effect W 0 26 Abort Queue Write 1 to this bit to abort the current transaction pending on the transaction controller Writing 0 has no e...

Page 62: ... the current transaction and write the status back to the transaction entry in memory on Link Error Set to 0 not to abort R W 0 7 to 6 Reserved None 0 8 Send a SYNC without DVALID after this transaction is finished Set to 1 to send set to 0 not to send Do not set both bits 8 and 9 R W 0 9 Send a SYNC with DVALID after this transaction is finished Set to 1 to send set to 0 not to send Do not set bo...

Page 63: ... words 11 to swap 32 bit words and bytes R W 0 28 Reserved None 0 29 Interrupt Write 1 to interrupt on transfer complete Write 0 otherwise R W 0 30 Go Set to 1 to start this transaction 0 to stop it If it is a chained transaction the first action is to fetch the chain entry R W 0 31 Done A 1 indicates this channel is currently idle A 0 indicates a DMA is in progress R 0 Send Next Chain Entry CNEXT...

Page 64: ...21 Reserved None 0 24 Enable Queue A 1 enables the queue to fetch transaction entries Setting this bit to 0 pauses the transaction queue R W 0 25 Reset Queue Write 1 to set the consumer and producer indices to 0 Writing 0 has no effect W 0 26 Abort Queue Write 1 to this bit to abort the current transaction pending on the transaction controller Writing 0 has no effect W 0 27 Stop on SYNC Set to 1 t...

Page 65: ...status back to the transaction entry in memory on SYNC Set to 0 not to abort R W 0 5 Abort Writeback on Link Error Set to 1 to abort the current transaction and write the status back to the transaction entry in memory on Link Error Set to 0 not to abort R W 0 9 to 6 Reserved None 0 10 Received SYNC without DVALID R 0 11 Received SYNC with DVALID Convert SYNC must be enabled in the Link Control reg...

Page 66: ... bit words 11 to swap 32 bit words and bytes R W 0 28 Reserved None 0 29 Interrupt Write 1 to interrupt on transfer complete Write 0 otherwise R W 0 30 Go A 1 starts this transaction A 0 stops it If it is a chained transaction the first action is to fetch the chain entry R W 0 31 Done A 1 indicates this channel is currently idle A 0 indicates a DMA is in progress R 0 Receive Next Chain Entry CNEXT...

Page 67: ... 7 1 7 2 Ordered Sets Used 7 1 7 3 Frames 7 3 7 3 1 Link Bandwidth 7 4 7 3 2 FPDP Signal Sample Rate 7 4 7 4 Data Transmission and Flow Control 7 5 FIGURES Figure 7 1 VITA 17 1 Framing Protocol 7 3 TABLES Table 7 1 Ordered Set Mapping 7 2 Table 7 2 Maximum Sustained Throughput 7 4 Table 7 3 Sampling Frequencies 7 4 ...

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Page 69: ...4096 words can be used 7 2 Ordered Sets Used Fibre Channel denotes a certain mapping of the transmission words in the 8B 10B protocol to be ordered sets which denote special control information for Fibre Channel These same ordered sets are used in VITA 17 1 but are assigned different meaning There are eighteen ordered sets used by SL240 to denote different information Twelve of these ordered sets ...

Page 70: ...Start of Frame PIO1 1 PIO2 1 DIR 0 SOFf SOF Start of Frame PIO1 1 PIO2 1 DIR 1 EOFt SEOF Status EOF FIFO Overflow 0 NRDY 0 EOFdt SEOF Status EOF FIFO Overflow 0 NRDY 1 EOFa SEOF Status EOF FIFO Overflow 1 NRDY 0 EOFn SEOF Status EOF FIFO Overflow 1 NRDY 1 EOFni MEOF Mark EOF EOF for a SYNC frame EOFdti FEOF Frame EOF EOF for a normal data frame R_RDY SWDV SYNC with DATA Valid Says that the next fr...

Page 71: ...output of the Transmit FIFO the current frame is terminated and the proper SYNC frame SYNC with data or SYNC without data is sent Figure 7 1 shows the four types of frames and the ordered set placement within those frames Figure 7 1 VITA 17 1 Framing Protocol IDLE SOF CRC GO STOP SEOF FEOF IDLE Fiber Frame IDLE SOF CRC GO STOP SEOF FEOF 1 To 512 4 Byte Data Words Maximum 2048 Bytes Data Fiber Fram...

Page 72: ...ode Master bit 1 SL100 105 02 MB s 105 22 MB s 104 41 MB s 104 61 MB s SL240 247 10 MB s 247 58 MB s 245 68 MB s 246 15 MB s NOTE The Copy Master Mode is located in the Link Control register 7 3 2 FPDP Signal Sample Rate The states of the FPDP signals PIO1 PIO2 DIR and NRDY are transmitted across the link at varying rates The worst case rate at which these signals are sampled is for CRC checked fi...

Page 73: ...anges Curtiss Wright Controls SL100 SL240 boards use the same protocol when transmitting from either end to allow the link to operate bi directionally Since these data streams are independent the maximum throughput on the link would be 210 MB s 105 MB s direction for SL100 or 494 MB s for SL240 The receiver should transmit the STOP signal when it has space for the data contained in 20 km of fiber ...

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Page 75: ... 2 5 SL100 FPDP Ordering Information 8 2 8 2 6 33 MHz SL240 PMC Ordering Information 8 2 8 2 7 33 MHz SL240 PCI Ordering Information 8 2 8 2 8 66 MHz SL240 PMC Ordering Information 8 2 8 2 9 66 MHz SL240 PCI Ordering Information 8 2 8 2 10 SL240 FPDP Ordering Information 8 2 8 2 11 Short Wavelength Multimode Fiber Optic Cables 8 3 8 2 12 Long Wavelength Single mode Fiber Optic Cables 8 4 8 2 13 HS...

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Page 77: ... 1 Table 8 3 66 MHz SL100 PMC 8 1 Table 8 4 66 MHz SL100 PCI 8 1 Table 8 5 66 MHz SL100 FPDP 8 2 Table 8 6 33 MHz SL240 PMC 8 2 Table 8 7 33 MHz SL240 PCI 8 2 Table 8 8 66 MHz SL240 PMC 8 2 Table 8 9 66 MHz SL240 PCI 8 2 Table 8 10 SL240 FPDP 8 2 Table 8 11 LC to LC 8 3 Table 8 12 LC to ST 8 3 Table 8 13 SC to LC 8 3 Table 8 14 LC to LC 8 3 Table 8 15 SC to LC 8 3 Table 8 16 Shielded 150 Ohm Quad ...

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Page 79: ...M4MWB04 00 SL100 PMC 850 nm SFP laser 5 V PCI signaling voltage FHK5 PM4MWB04 R1 SL100 PMC 850 nm SFF laser 5 V PCI signaling voltage Rugged Level 1 8 2 2 33 MHz SL100 PCI Ordering Information Table 8 2 33 MHz SL100 PCI Order Number Description FHK5 PC4MWB04 00 SL100 PCI 850 nm SFP laser 5 V PCI signaling voltage 8 2 3 66 MHz SL100 PMC Ordering Information Table 8 3 66 MHz SL100 PMC Order Number D...

Page 80: ... Order Number Description FHK7 PC6MWB04 00 SL240 PCI 850 nm SFP laser 5 V PCI signaling voltage 8 2 8 66 MHz SL240 PMC Ordering Information Table 8 8 66 MHz SL240 PMC Order Number Description FHF7 PM6MWB04 00 SL240 PMC 850 nm SFP laser 3 3 V PCI signaling voltage FHF7 PM6MWB04 R1 Rugged Level 1 SL240 PMC 850 nm laser 3 3 V PCI signaling voltage 8 2 9 66 MHz SL240 PCI Ordering Information Table 8 9...

Page 81: ...HAC M2LCxxxx 00 Custom LC LC Table 8 12 LC to ST Simplex Part Number Duplex Part Number Length Cable End 1 Cable End 2 FHAC M1LCST03 00 FHAC M2LCST03 00 3 meters LC ST FHAC M1LCST05 00 FHAC M2LCST05 00 5 meters LC ST FHAC M1LCST10 00 FHAC M2LCST10 00 10 meters LC ST FHAC M1LCST20 00 FHAC M2LCST20 00 20 meters LC ST FHAC M1LCST30 00 FHAC M2LCST30 00 30 meters LC ST FHAC M1LCSTxx 00 FHAC M2LCSTxx 00...

Page 82: ...LC5000 00 5 meters LC LC FHAC S1LC1001 00 FHAC S2LC1001 00 10 meters LC LC FHAC S1LC2001 00 FHAC S2LC2001 00 20 meters LC LC FHAC S1LC3001 00 FHAC S2LC3001 00 30 meters LC LC FHAC S1LCxxxx 00 FHAC S2LCxxxx 00 Custom LC LC Table 8 15 SC to LC Simplex Part Number Duplex Part Number Length Cable End 1 Cable End 2 FHAC S1SCLC01 00 FHAC S2SCLC01 00 1 meter SC LC FHAC S1SCLC03 00 FHAC S2SCLC03 00 3 mete...

Page 83: ...0 5 m HSSDC2 cable equalized FHAC Q2H11001 00 10 m HSSDC2 cable equalized FHAC Q2H12001 00 20 m HSSDC2 cable equalized FHAC Q2H12501 00 25 m HSSDC2 cable equalized FHAC Q2H13001 00 30 m HSSDC2 cable equalized 8 2 14 HSSDC2 Copper Media Interface 2 5 Gbps Shielded 100 Ohm Shielded Quad copper cable with HSSDC2 InfiniBand connectors for use with the HSSDC2 copper media interface Table 8 17 Shielded ...

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Page 85: ... 9 5 Parallel FPDP Signal Timing 9 6 FIGURES Figure 9 1 Example Configuration With Multiple VME FPDP Cards Connected 9 2 Figure 9 2 Parallel FPDP Interface Timing Diagram 9 7 Figure 9 3 FPDP Timing Diagrams Showing the Use of Framing 9 8 TABLES Table 3 1 HSSDC2 Receptacle Pin Assignments for SL100 3 5 Table 9 1 Parallel FPDP Timing Specifications 9 9 Table 9 2 FPDP Transmitter Interface Timing Spe...

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Page 87: ...de the required bandwidth and latency at all times because of bus contention The primary bus must also handle other tasks such as system control The FPDP bus provides a solution to this problem Using FPDP two or more cards are connected by a simple parallel synchronous interface using 80 conductor ribbon cable running across the cards front panels or through a 1 0625 Gbps or 2 5 Gbps serial interf...

Page 88: ...sting bus bandwidth No bus contention is possible because there is only one transmitter No special backplane is required FPDP allows connections from VME chassis to VME chassis Systems may have multiple FPDP buses and thus provides scaleable bandwidth Multiple FPDP busses may coexist in one chassis Throughput can be accurately computed in the design stage Little software development is required to...

Page 89: ...ne FPDP RM may exist on an FPDP bus FPDP RECEIVER FPDP R An FPDP R is a device that receives data from the FPDP bus synchronously with the timing signals provided by the FPDP TM As opposed to the FPDP RM this device does not terminate any bus signals on parallel FPDP Multiple FPDP R devices may exist on an FPDP bus 9 3 Parallel FPDP Theory of Operation 9 3 1 Clock Signals A single FPDP TM generate...

Page 90: ...in order to correctly receive data SINGLE FRAME DATA Synchronization must occur prior to data to which it applies Synchronization occurs between data blocks SYNC must be asserted before DVALID is asserted Synchronization occurs infrequently perhaps only once When single frame data is transmitted onto the FPDP bus the FPDP TM must assert a SYNC pulse before valid data starts being transmitted Valid...

Page 91: ...the last data word in the block before is transferred SYNC must be asserted at the end of the data block while DVALID is still asserted Because synchronization occurs at the end of the data block the first data block will not be synchronized Synchronization occurs frequently Data frames may vary in size For dynamic size repeating frame data the behavior of the SYNC pulse is the same as for fixed s...

Page 92: ...DP RM and FPDP R devices The FPDP RM and FPDP R devices must assert NRDY when they are not ready to accept data and must de assert NRDY otherwise The NRDY signal is asynchronous to the STROBE clock and should be double synchronized by the FPDP TM before being used in order to avoid metastability problems As required by the Front Panel Data Port Specifications ANSI VITA 17 1998 the FPDP TM transmit...

Page 93: ...ID VALID VALID VALID VALID VALID VALID VALID XXXX XXXX XXXX DVALID D 31 0 SYNC XXXX VALID SUSPEND D 31 0 DVALID STROBE VALID VALID VALID VALID VALID XXXX VALID VALID XXXX XXXX VALID VALID VALID NRDY PSTROBE PSTROBE STROBE 1 2 4 3 Figure 9 2 Parallel FPDP Interface Timing Diagram ...

Page 94: ...XXXX XXXX STROBE DVALID D 31 0 SYNC XXXX VALID SYNC D 31 0 DVALID STROBE VALID VALID VALID VALID VALID VALID VALID XXXX XXXX XXXX XXXX XXXX XXXX VALID VALID VALID VALID A SINGLE FRAME DATA B FIXED SIZE AND DYNAMIC SIZE REPEATING FRAME DATA 1 2 2 1 Figure 9 3 FPDP Timing Diagrams Showing the Use of Framing ...

Page 95: ...eter Description At Transmitter End of Cable At Receiver End of Cable FPDP Clock Used 1 Data DVALID SYNC setup time 6 0 ns min 5 0 ns min TTL 1 Data DVALID SYNC setup time 5 5 ns min 4 5 ns min PECL 2 Data DVALID SYNC hold time 12 8 ns min 11 8 ns min TTL 2 Data DVALID SYNC hold time 12 0 ns min 11 0 ns min PECL Table 9 2 FPDP Transmitter Interface Timing Specifications Parameter Description Min M...

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Page 97: ...ting 5 5 connection point to point 4 3 connections broadcast 2 1 2 4 intrasystem 2 5 point to point 2 1 2 4 connector duplex LC 2 5 3 4 5 6 5 7 HSSDC2 3 5 8 5 simplex LC 3 4 Connector HSSDC2 5 7 connectors fiber optic 3 4 control registers 4 6 copy master 7 5 copy master mode 6 8 7 5 copy mode master 7 5 CRC 4 3 4 6 6 6 6 7 7 5 data dynamic size repeating frame 9 4 9 5 fixed size repeating frame 9...

Page 98: ...e Serial FPDP specification 6 7 9 3 9 4 9 7 transmit master 4 3 transmitter port 9 3 FPDP cable length 2 7 FPGA logic 6 8 6 9 frame 6 8 7 1 7 3 7 5 checksum 2 4 control words 4 2 data 7 4 IDLE 7 4 SYNC with data 7 4 SYNC without data 7 4 types 7 4 frame size maximum 4 6 frame size 4 2 framing state machine 4 2 front panel data port 9 1 GLX4000 2 6 GLX4000 Physical Layer Switch 2 6 2 10 host bus in...

Page 99: ...tage 5 1 5 2 5 3 5 4 operation 4 5 6 7 6 12 6 14 6 15 64 bit 2 4 asynchronous 9 6 hardware 1 1 loop 4 1 4 2 4 5 non loop 4 4 normal 6 17 6 18 point to point 2 4 receive 4 1 theory 4 1 transmit 4 2 Order 8 5 order numbers multimode FO 8 3 singlemode fiber optic 8 4 ordered set 7 4 ordered sets 4 3 4 4 6 8 7 1 7 2 7 5 parallel port unidirectional 2 1 PCI address 6 14 6 15 6 16 6 17 6 18 6 20 PCI bus...

Page 100: ...DV 4 2 SYNC 4 2 4 5 6 6 6 7 6 11 7 1 7 3 7 4 9 5 SYNC with DVALID 6 6 6 18 SYNC without DVALID 6 8 6 18 timing 9 3 signaling voltage 3 3 V PCI 8 1 8 2 5 V PCI 8 1 8 2 single board computer 2 1 specifications average current 5 1 peak current 5 1 speed of light 7 6 status information 4 5 status retrieval 2 4 storage altitude 5 5 storage humidity 5 5 storage temperature 5 1 5 2 5 3 5 4 5 5 STROBE clo...

Page 101: ...ransfer rate link 7 1 maximum 9 3 transmission distance 9 3 transmission rates link 2 7 transmit interface 9 10 transmit wavelength 5 6 5 7 unpack 3 1 vibration 5 5 video transmission applications 2 9 virtual FPDP bus 4 2 VITA 17 1 4 3 4 4 7 1 7 2 7 4 9 1 VME chassis 9 2 weight 5 1 5 2 5 3 5 4 word swapping 6 4 ...

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