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Preliminary Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

1

Copyright 

 Cirrus Logic, Inc. 1999

(All Rights Reserved)

Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222   FAX: (512) 445 7581
http://www.crystal.com

 

CS5521
CS5523

2- or 4-Channel 16-Bit Buffered 

∆Σ

 Multi-Range ADC

Features

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Delta-Sigma A/D Converter

— Linearity Error: 0.0015%FS

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Buffered Bipolar/Unipolar Input Ranges 

— 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V

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Chopper Stabilized Instrumentation Amplifier

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On-Chip Charge Pump Drive Circuitry

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Differential Multiplexer

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Conversion Data FIFO

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Programmable/Auto Channel Sequencer

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2-Bit Output Latch

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Simple three-wire serial interface

— SPI™ and Microwire™ Compatible
— Schmitt Trigger on Serial Clock (SCLK)

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Output Settles in One Conversion Cycle 

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50/60 Hz ±3 Hz Simultaneous Rejection

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Buffered V

REF

 with +5 V Input Capability

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System and Self-Calibration with R/W 
Registers per Channel

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5 V Analog Supply
+3.0 V or +5 V Digital Supply

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Power Consumption: 5.5 mW
- 1.8 mW in 1 V, 2.5 V and 5 V input ranges

General Description

The 16-bit CS5521/23 are highly integrated 

∆Σ

 A/D con-

verters which include an instrumentation amplifier, a PGA
(programmable gain amplifier), a multi-channel multiplexer,
digital filters, and self and system calibration circuitry.

The chips are designed to provide their own negative
supply which enables their on-chip instrumentation am-
plifiers to measure bipolar ground-referenced signals
less-than or equal to ±100 mV.

The digital filters provide programmable output update
rates of 1.88 Hz, 3.76 Hz, 7.51 Hz, 15 Hz, 30 Hz,
61.6 Hz, 84.5 Hz, and 101.1 Hz when operating from a
32 kHz crystal. The CS5521/23 are capable of producing
output update rates up to 303 Hz with a 100kHz clock.
The filters are designed to settle to full accuracy for the
selected output update rate within one conversion cycle.
When operated at word rates of 15 Hz or less, the digital
filters reject both 50 and 60 Hz line interference 

±

3 Hz

simultaneously.

Low power, single conversion settling time, programma-
ble output rates, and the ability to handle negative input
signals make these single supply products ideal solu-
tions for isolated and non-isolated applications.

ORDERING INFORMATION

See page 33.

VD+

DGND

Differential 

4th order 

delta-sigma 

modulator

Digital Filter

Calibration

Register

Calibration 

µ

C

VA+

Control
Register

   XIN  XOUT

Programmable

Gain

AGND

CS

SCLK

SDI

SDO

VREF-

 CPD

 NBV

 X20

A0 A1

Calibration

Memory

VREF+

Latch

AIN1-

AIN1+

AIN2+

AIN2-

 +

 -

Output
Register

 X1

 X1

 X1

MUX

CS5523

Shown

AIN3-

AIN3+

AIN4+

AIN4-

C lock

Gen.

MAR ‘99

DS317PP2

Summary of Contents for CS5521-AP

Page 1: ...which include an instrumentation amplifier a PGA programmable gain amplifier a multi channel multiplexer digital filters and self and system calibration circuitry The chips are designed to provide th...

Page 2: ...duct information describes products which are in production but for which full characterization data is not yet available Advance product information describes products which are in development and su...

Page 3: ...Command and Data Word Timing 15 Multiplexer Configuration 22 Input models for AIN and AIN pins for each range 24 Input model for VREF and VREF pins 24 Self Calibration of Offset Low Ranges 26 Self Ca...

Page 4: ...t ranges 100 mV and output rates 61 6 Hz 16 384 kHz chopping frequency is used Parameter Min Typ Max Unit Accuracy Resolution 16 Bits Linearity Error 0 0015 0 003 FS Bipolar Offset Note 3 1 2 LSB16 Un...

Page 5: ...mmon Mode Rejection dc 50 60 Hz 120 120 dB dB Input Capacitance 10 pF CVF Current on AIN or AIN Note 5 Range 25 mV 55 mV or 100 mV Range 1 V 2 5 V or 5 V 100 10 300 pA nA System Calibration Specificat...

Page 6: ...0 VD 1 0 VD 1 0 V V V Low Level Output Voltage All Pins Except CPD and SDO Iout 1 6 mA CPD Iout 2 mA SDO Iout 5 0 mA VOL 0 4 0 4 0 4 V V V Input Leakage Current Iin 1 10 A 3 State Leakage Current IOZ...

Page 7: ...ed at these extremes Parameter Symbol Ratio Unit Modulator Sampling Frequency fs XIN 4 Hz Filter Settling Time to 1 2 LSB Full Scale Step ts 1 fout s Parameter Symbol Min Typ Max Unit DC Power Supplie...

Page 8: ...scillator XIN 30 32 768 100 kHz Master Clock Duty Cycle 40 60 Rise Times Note 20 Any Digital Input Except SCLK SCLK Any Digital Output trise 50 1 0 100 s s ns Fall Times Note 20 Any Digital Input Exce...

Page 9: ...7PP2 9 CS SCLK t0 t2 t1 t3 t6 Continuous Running SCLK Timing Not to Scale CS SCLK MSB MSB 1 LSB SDI t3 t4 t5 t1 t2 t6 SDI Write Timing Not to Scale CS SCLK MSB MSB 1 LSB SDO t7 t8 t1 t2 t9 SDO Read Ti...

Page 10: ...23 A D converters are designed to op erate from a single 5 V analog supply with several different input ranges See the Analog Character istics section on page 3 for details Figure 1 illustrates the CS...

Page 11: ...ts Figure 5 illustrates the CS5521 23 connected to measure the output of a ratiometric differential bridge transducer while operating from a single 5 V supply 5V NBV 30 1K 34 8K 2N5087 or similar 5V 2...

Page 12: ...er for each input channel The serial port also includes a programmable channel sequencer which can se quence up to 8 channels to be converted The se quencer consists of channel setup registers CSRs wh...

Page 13: ...s SCLK is designed with a Schmitt trigger input to allow an optoisola tor with slower rise and fall times to directly drive the pin Additionally SDO is capable of sinking or sourcing up to 5 mA to dir...

Page 14: ...ster Conversion Data FIFO read only Channel Set up Registers register is 48 bits long for CS5521 register is 96 bits long for CS5523 Reserved Reserved Table 1 Command Set with MSB 0 D7 MSB D6 D5 D4 D3...

Page 15: ...LKs CS SCLK SDI Data Time 24 SCLKs Read Cycle SDO MSB LSB Command Time 8 SCLKs 8 SCLKs Clear SDO Flag SDO SCLK SDI Data Time 24 SCLKs MSB LSB td XIN OWR clock cycles for each conversion except the fir...

Page 16: ...D23 D11 D22 D10 register bits D21 D9 Not Used NU 0 R Must always be logic zero D20 D8 D19 D7 Channel Select CS1 CS0 00 01 10 11 R Select physical channel 1 Select physical channel 2 Select physical c...

Page 17: ...Refer to Calibration Protocol for details D15 Not Used NU 0 R Must always be logic 0 D14 D12 Depth Pointer DP2 DP0 000 111 R When writing or reading the CSRs these bits DP2 DP0 determine the number o...

Page 18: ...nel While in this mode the user may choose to acquire only the conversions required for his application as SDO rises and falls to indicate the availability of a new conversion To exit this conversion...

Page 19: ...is case SDO rises and falls once a new set of conversions is complete to indicate that a new set of data is ready to acquire or 3 read the conversion data FIFO and remain in this mode this is accom pl...

Page 20: ...nversions on six logical channels The order in which the channels are converted is 4 1 4 2 4 3 SDO falls after physical channel 3 is converted To acquire the 6 conversions 8 SCLKs with SDI 0 are re qu...

Page 21: ...sical chan nel 4 in this example SDO falls after physical channel 4 is converted To read the conversion 32 SCLKs are then required Once acquired the serial port returns to the command mode Example 5 T...

Page 22: ...1 23 can accommodate full scale ranges other than 25 mV 55 mV 100 mV 1 V 2 5 V and 5 V by performing a system calibration within the limits specified See the Calibration section for more details Anoth...

Page 23: ...the AIN and AIN pins remains constant for the three low level mea surement ranges 25 mV 55 mV and 100 mV The input current is lowest with the CFS bits cleared to logic 0s Note Residual noise appears i...

Page 24: ...s of the device For a single ended refer ence voltage such as the LT1019 2 5 the reference voltage is input into the VREF pin of the convert er and the VREF pin is grounded The differential voltage be...

Page 25: ...ange the converter s gain er ror can not be completely calibrated out This is due to the lack of an accurate full scale voltage internal to the chips The 2 5 V range is an exception be cause the exter...

Page 26: ...exceed 3 9999998 see the discussion of operating limits on input span under the Analog Input and Limita tions in Calibration Range sections The above conditions require the full scale input voltage to...

Page 27: ...it 2 s complement Cg Gain calibration register value 24 bit integer Calibration Tips Calibration steps are performed at the output word rate selected by the WR2 WR0 bits of the configu ration register...

Page 28: ...te of the converter as shown in Table 4 The word rates indicated in the table assume a master clock of 32 768 kHz Upon reset the converter is set to operate with an output word rate of 15 0 Hz Clock G...

Page 29: ...The power save modes are entered whenever the PS R bit of the configuration register is set to logic 1 The particular power save mode entered depends on state of bit D11 PSS the Power Save Select bit...

Page 30: ...medi ately adjacent to the digital portion of the chip If separate digital VD and analog VA supplies are used it is recommended that a diode be placed between them the cathode of the diode should poin...

Page 31: ...LOGIC OUTPUT NEGATIVE BIAS VOLTAGE DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT POSITIVE ANALOG POWER ANALOG GROUND CRYSTAL IN CHIP SELECT VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIFFER...

Page 32: ...input pins into the CS5521 and CS5523 devices VREF VREF Voltage Reference Input Fully differential inputs which establish the voltage reference for the on chip modulator NBV Negative Bias Voltage Inp...

Page 33: ...ansition from the ideal VREF VREF 3 2 LSB Units are in LSBs Unipolar Offset The deviation of the first code transition from the ideal 1 2 LSB above the voltage on the AIN pin When in unipolar mode U B...

Page 34: ...el 3 Dimension E does not include mold flash INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0 155 0 180 3 94 4 57 A1 0 020 0 040 0 51 1 02 b 0 015 0 022 0 38 0 56 b1 0 050 0 065 1 27 1 65 c 0 008 0 015 0 20...

Page 35: ...sion E does not include mold flash INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0 155 0 180 3 94 4 57 A1 0 020 0 040 0 51 1 02 b 0 014 0 022 0 36 0 56 b1 0 040 0 065 1 02 1 65 c 0 008 0 015 0 20 0 38 D 1...

Page 36: ...material condition Dambar intrusion shall not reduce dimension b by more than 0 07 mm at least material condition 3 These dimensions apply to the flat section of the lead between 0 10 and 0 25 mm fro...

Page 37: ...material condition Dambar intrusion shall not reduce dimension b by more than 0 07 mm at least material condition 3 These dimensions apply to the flat section of the lead between 0 10 and 0 25 mm fro...

Page 38: ...cation may be copied reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photographic or otherwise without the prior written consent of Cirrus Logi...

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