CS5521 CS5523
DS317PP2
19
tion register determine how many conversions are
performed and hence must be initialized before this
conversion mode is entered. Upon completion of
the conversions, SDO falls to indicate that the con-
version data set is ready to be read. To read the con-
versions from the conversion data FIFO, the user
must first issue 8 SCLKs to clear the SDO flag. To
read the conversions, the user must then supply
24x(N) SCLKs. N is defined here as the number
of logical channels being converted which is the
decimal equivalent of depth + 1. For example, if
DP2-DP0 = ‘010’, N = (2+1) = 3. To return to the
command mode, the user must read all the conver-
sion data from the FIFO because the serial port re-
mains in data mode during the conversions and
during the read of the data. Whether ‘00000000’ or
‘11111111’ is provided to the SDI during the 8
SCLKs needed to clear the SDO flag, the serial port
returns to the command mode after the conversion
data FIFO is read.
MC = 1 LP = 1 RC = 0
Based on information provided in the CSRs, multi-
ple conversions are repeatedly performed on the
physical channels referenced by the logical chan-
nels of the CSRs. This conversion mode is similar
to the conversion mode when MC=1, LP=0, and
RC=X. Once a conversion data set is converted the
conversions are stored in the conversion data FIFO.
The only exception is that the converter then re-
turns to the top of the CSRs (i.e. to logical channel
one of CSR #1) and repeats. As before, SDO falls
to indicate when a data set is compete. Once SDO
falls, the user has three options: 1) exit after reading
the conversion data FIFO; this is accomplished by
providing SDI ‘11111111’ during the first 8
SCLKS and then giving 24xN more SCLKs to ac-
quire the conversion data; 2) provide no SCLKs
and remain in this mode without reading the data;
in this case, SDO rises and falls once a new set of
conversions is complete to indicate that a new set
of data is ready to acquire; or 3) read the conversion
data FIFO and remain in this mode; this is accom-
plished by providing SDI with ‘00000000’ during
the first 8 SCLKs and then giving 24xN more
SCLKs to read the conversion data; the user must
finish reading the FIFO before the first logical
channel of CSR #1 finishes a new conversion.
MC = 1 LP = 1 RC = 1
Based on information provided in the CSRs, multi-
ple conversions are performed repeatedly on the
logical channel of the CSR. This mode is similar to
the conversion mode when MC=1, LP=1, and
RC=0. The only exception is that the converter
stops and waits for the conversion data FIFO to be
emptied before new conversions are started. As be-
fore SDO falls when a data set is complete. Once
SDO falls, the user has two options: 1) exit after
emptying the FIFO; this is accomplished by pro-
viding SDI ‘11111111’ during the first 8 SCLKs
and then giving 24xN more SCLKs to read the con-
version data; or 2) empty the conversion data FIFO
and remain in this mode; this is accomplished by
providing SDI with ‘00000000’ during the first 8
SCLKs and then giving 24xN more SCLKs to read
the conversion data. After the FIFO is emptied, the
converter returns to the top of the CSRs (i.e. to log-
ical channel one of CSR#1) and repeats.
Calibration Protocol
To perform a calibration the user must send a com-
mand byte with its MSB=1, its pointer bits (CPB2-
CPB0) set to address the desired logical channel to
be calibrated, and the appropriate calibration bits
(CC2-CC0) set to choose the type of calibration to
be performed. Proper calibration assumes that the
CSRs have been previously initialized because the
information concerning the physical channel, its
filter rate, gain range, and polarity, comes from the
channel-setup register being addressed by the
pointer bits in the command byte.
Once the CSRs are initialized all future calibrations
can be performed with one command byte. Once a
