Creotech FMC masterFIP User Manual Download Page 21

- 20 -

 

 

 

RST_N line 

o

 

The RST_N line does not stall the transmission/ reception of data. It resets the TX_ERR 
and  WDG_N  lines.  Following  from  the  WDG_N test  described  above,  we  activate  the 
fd_rst_n_o line and check that the td_wdgn_i goes inactive. 

Possible errors: 

 

Frame format, Frame size, Number of bytes, CRC, Preamble, Data field, Data control field 

o

 

Incorrectly connected cables 

o

 

Wrong speed configuration of SSSB231 (IC14) 

o

 

Wrong speed of the nanoFIPdiag box 

o

 

Faulty transformer (TR1) 

o

 

Faulty SSSB231 (IC14) 

o

 

Faulty soldering of FMC connector 

 

CD_N during transmission, CD_N during idle, TX_ERR idle, TX_ERR during normal transmission, 
TX_ERR  corrupted  transmission,  WDG_N  during  correct  transmission,  WDG_N  during  long 
transmission, WDG_N during idle, RST_N 

o

 

Faulty SSSB231 (IC14) 

o

 

Faulty soldering of IC14 

o

 

Faulty soldering of FMC connector 

Test 03

 

Lemo connector and buffer SN74LVC8T245PW (IC1) input/output test. 

The table below describes the series of tests performed regarding the SN74LVC8T245PW (IC1) and its 
associated pins. In bold we highlight the signal that mostly defines the output. 

During all tests FPGA IO connected to EXT_SYN line is kept in High-Z state with internal pulldown resistor. 
EXT_SYNC line is connected to USB Relay Box with Lemo cable to channel 1, that is connected to Vref 
voltage. Voltage value is controlled via USB. 

Table 5: Sequence of actions to test the SN74LVC8T245PW (IC1) 

Test#  OEn 

EXT_SYN
C_DIR 

EXT_SYNC
_TERM_E

USB 
Relay 
Box 

Expected Result 

Comment 

#1 

0 (input) 

Low

 

Read "0" from the FPGA 
EXT_SYN pin forced by 
USB Relay Box 

 

#2 

High

 

Read "1" from the FPGA 
EXT_SYN pin forced by 
USB Relay Box.  

Value read by FPGA follows 
USB Relay Box voltage. 

LEMO connector is checked. 

#3 

0

 

High 

Read "1" from the FPGA 
EXT_SYN pin forced by 
USB Relay Box. 

 

#4 

0

 

High 

Read "0" from the FPGA 
EXT_SYN pin forced by 
termination pulldown. 

Value read by FPGA is pulled 
low by termination no 
matter USB Relay Box 
voltage. 

Termination line is checked. 

#5 

0

 

Low

  

Read "0" from the FPGA 
EXT_SYN pin forced by 

 

Summary of Contents for FMC masterFIP

Page 1: ...FMC masterFIP Production Test Suite User Manual Creotech Instruments SA Jan 2018 Version 4 0...

Page 2: ...name ipmi part EDA 03098 V4 3 0 08 03 2017 Marek Gumi ski Update to board version V3 removed ADC tests modified EXT_SYNC tests 2 0 16 11 2016 Evangelia Gousiou Changes for V2 version of the board remo...

Page 3: ...1 Introduction 3 2 FMC masterFIP Board Functionality 9 3 PTS Functionality Tests 10 4 Log files retrieval 11 5 Custom cable preparation 12 6 First Time Setup 13 7 Testing Procedure 15 8 Common Causes...

Page 4: ...signed for the Open Hardware Repository but it proved to be adaptable to other boards It assures that the boards comply with a minimum set of quality rules in terms of soldering mounting and fabricati...

Page 5: ...tom cable Schematic shown in Figure 9 picture of real component in Figure 6 1x LEMO miniDsub9 custom cable Schematic shown in Figure 9 picture of real component in Figure 6 nanoFIPDiag nanoFIPdiag ver...

Page 6: ...The SPEC carrier board provides access to the PCIe interface of the computer The computer hosts the FMC masterFIP PTS software which provides the automated testing environment Figure 2 SPEC DAC DDS c...

Page 7: ...o automate cable reconnections Figure 4 USB relay box 1 The nanoFIPdiag is used to verify the WorldFIP bus communication by answering to WorldFIP question frames Note that the nanoFIPdiag speed versio...

Page 8: ...7 Custom cables are used to connect the FMC masterFIP to the nanoFIPdiag via the USB relay box Figure 6 Custom cables One standard Lemo00 Lemo00 cable is also required Any length may be used...

Page 9: ...tervention needs to be done by the operator e g scan the board s barcode check the font panel LED the interventions are explicitly signaled by the FMC masterFIP PTS software and this manual At the end...

Page 10: ...t in 2009 it was decided to insource this technology at CERN Figure 8 Bottom top and front views of the masterFIP board The FMC masterFIP mezzanine board is tested while mounted on a SPEC carrier boar...

Page 11: ...ed for all the tests loaded at test00 Table 4 List of tests Test Short Description Operator s Intervention 00 Loads firmware tests mezzanine presence verify speed version Yes 01 Test front panel LED s...

Page 12: ...ory key in to the computer o Wait until Ubuntu mounts automatically the device o Using the file explorer navigate to Desktop masterFIP_log fmcmasterfip directory o Select all the zip files right click...

Page 13: ...re is no need to use the WorldFIP protocol specified cable The following schematics are made with following markings yellow box connector type is given inside the box green box pins of Dsub connector...

Page 14: ...uter cover Confirm that the USB relay box is mounted on the upper side of the computer cover Figure 10 Top side of the computer cover 3 Screw the SPEC board on the top side of the computer cover as Fi...

Page 15: ...nment through the following commands Please note that the test environment may be installed in any path The installation sequence then makes sure that the top directory is called fmcmasterfip test env...

Page 16: ...diag speed version should match the masterFIP speed version Connecting Dsub9 LEMO cable o connect the Dsub9 plug to the nanoFIPdDiag o connect the Positive LEMO plug to CH5 of the USB Relay Box o conn...

Page 17: ...for a second barcode in case the manufacturer has a different serial number system Scan the second barcode and press ENTER or if there is none just press ENTER The program will automatically execute t...

Page 18: ...rding issues that might affect each test USB calibration box not detected Verify that the USB cable is well connected between the PC and the box itself Verify with lsmod that the cp210x driver is moun...

Page 19: ...uild o Make sure that all drivers were loaded successfully Firmware loader failure No access to masterfip core Wrong bitstream type loaded o Make sure that installation procedure was done according to...

Page 20: ...e masterFIP sends an ID_DAT 147F which triggers the nanoFIPdiag to reply with an RP_DAT The fd_txer_i line is expected to be inactive during this transmission and reception In the FPGA a counter is co...

Page 21: ...The table below describes the series of tests performed regarding the SN74LVC8T245PW IC1 and its associated pins In bold we highlight the signal that mostly defines the output During all tests FPGA I...

Page 22: ...t in Hi Z state with internal pulldown If switching buffer direction didn t work value read from FPGA IO would follow USB Relay Box voltage as shown in previous tests EXT_SYNC_DIR line checked Possibl...

Page 23: ...al SERIAL part EDA 03098 V4 SPEED o name FmcMasterFip o speed number from 0 31 25k speed version to 3 5M speed version Possible errors EEPROM communication EEPROM content o EEPROM might be broken or b...

Reviews: