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Test 02
This test performs SSSB231 FieldDrive (IC14) tests. The following points are tested one-by-one as
described below.
FIP communication
o
The masterFIP sends a request frame asking for the presence of the nanoFIPdiag
(ID_DAT(147F)).
o
The PTS waits for the response RP_DAT and verifies that all the bytes of the frame
received by the masterFIP match the expected ones.
CD_N line
o
The CD_N line is expected to be inactive during bus idle. The test samples 10 times the
fd_rxcdn_i FPGA pin.
o
The CD_N line is expected to be active during frame reception. For this test the masterFIP
sends an ID_DAT(147F) which triggers the nanoFIPdiag to reply with an RP_DAT; the
fd_rxcdn_i line is expected to be active during the RP_DAT frame reception. In the FPGA
a counter is counting the transitions (falling edges) of the fd_rxcdn_i line. The test
expects to find the counter increased by two by the end of the RP_DAT frame.
TX_ERR line
o
The TX_ERR line is expected to be inactive when there is no transmission. The test
samples 10 times the fd_txer_i FPGA pin.
o
The TX_ERR line is expected to be inactive during normal frame transmission. For this
test the masterFIP sends an ID_DAT(147F) which triggers the nanoFIPdiag to reply with
an RP_DAT. The fd_txer_i line is expected to be inactive during this transmission and
reception. In the FPGA a counter is counting the transitions (rising edges) of the fd_txer_i
line. The test expects to find the counter at zero.
o
The TX_ERR line is expected to be active when the TXD line is stuck low or high. For this
test we set the fd_txd_o line to output a constant zero. At the same time we monitor
the counter that counts the fd_txer_i transitions and expect it increased.
WDG_N line
o
The WDG_N line is expected to be inactive when there is no transmission. The test
samples 10 times the fd_wdgn_i FPGA pin.
o
The WDG_N line is expected to be inactive during normal frame transmission. For this
test the masterFIP sends an ID_DAT(147F) which triggers the nanoFIPdiag to reply with
an RP_DAT. The fd_wdgn_i line is expected to be inactive during this transmission and
reception. In the FPGA a counter is counting the transitions (falling edges) of the
fd_wdgn_i line. The test expects to find the counter at zero.
o
The WDG_N line is expected to be active upon the transmission/reception of a very long
frame. For this test we trigger the transmission of a 1024 bytes frame. At the same time
we monitor the counter counting fd_wdgn_i transitions and expect it increased.
