
S280-75-2
19
Figure 28.
Form 3 tie board test points for internal minimum-trip signal (Table 4). For relationship of terminal location on the tie board, see
Figures 18 and 19.
Figure 27.
Form 3A tie board test points for internal dc-load-current signal
(Table 3). For relationship of terminal location on the tie board, see
figures 20 and 21.
88948KMA
TABLE 4
Tie Board Test Points for Minimum-Trip Signal
Figures 28, 29, and 30)
INTERNAL MINIMUM TRIP SIGNAL
To check the minimum-trip signal, measure the voltage at tie
board test points listed in Table 4.
Failures to get these signals are most likely due to troubles on
the phase-trip No. 2 or ground-trip No. 2 circuit boards or possi-
bly with the phase-trip No.1 or ground-trip No.1 boards. Battery
voltage below 21-Vdc will cause control misoperation of the min-
imum-trip, timing and trip signals of the control. Battery voltage
above 23 volts will operate the circuits correctly. Refer to
“Battery Maintenance,” page 35, for battery charging and testing
information.
Minimum
Terminal Position Voltage Reading Vdc
Trip
Form 3 Form 3A
120%
Signal
Minimum-
+Lead -Lead +Lead -Lead No Fault Trip*
Ph Seq. Ph Seq.
Phase
Min. Relay Min. Relay 25 or
0.30 Max.
Trip 7A
Trip 7A
Battery
Gnd. Seq. Gnd. Seq.
Ground
Min. Relay Min.
Relay 25 or 0.30 Max.
Trip 7A
Trip 7A
Battery
*Voltage reading will last only for the duration of the clearing time of the control
and recloser/simulator.
Summary of Contents for Kyle Type ME Series
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