6. BIOS Setup
SPI-8150-LVA, SPI-8151-LVA
55
Function description
Choice
SDRAM CAS Latency Time
You can select CAS latency time in HCLK
of 2/2 or 3/3. The system board designer
should set the values in this field, depends
on the DRAM installed specifications of the
installed DRAM or the installed CPU.
SDRAM Cycle Time Tras/Trc
This item sets the timing parameters for the
system memory such as the Tras and Trc.
SDRAM Cycle Time Tras/Trc
7/9 . . . . [ ]
5/7 . . . . [ ]
Auto . . . . [ ]
Move ENTER:Accept ESC:Abort
→
→
SDRAM RAS-to-CAS Delay
This item sets the timing parameters for the
system memory such as the CAS (Column
Address Strobe) and RAS (Row Address
Strobe).
SDRAM RAS to CAS Delay
3 . . . . [ ]
2 . . . . [ ]
Auto . . . . [ ]
Move ENTER:Accept ESC:Abort
→
→
SDRAM RAS Precharge Time
RAS# Precharge Timing
SDRAM must continually be refreshed or it
will lose its data. This option allows you to
determine the timing for RAS.
SDRAM RAS Precharge Time
3 . . . . [ ]
2 . . . . [ ]
Auto . . . . [ ]
Move ENTER:Accept ESC:Abort
→
→
System BIOS Cacheable
Selecting
Enabled
allows caching of the
system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance.
However, if any program writes to this
memory area, a system error may result.
