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Product Nomenclature and Function
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CPSN-CNT-3201I Reference Manual (Hardware)
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26
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4.
Other Functions
1.
Compare Register
Compare the count value of a corresponding channel with the compare register value. If these two
values match, set status bit "EQ" to "0" (remains 0 as long as they are in agreement). This register
can be set to any value from 0h to FFFFFFh. It is possible either to cause an interrupt or to output a
one-shot pulse to an external device when the two values match.
This register can be set to any value from 0h to FFFFFFh.
*The setting can be done on Web browser menu. Refer to the Reference Manual (Software) for setting
procedure.
2.
Digital Filter
The digital filter allows the counter to operate normally even when noise enters into pulses input to
the counter and/or into A-, B-, and Z-phase signals.
Operation Principle
The sampling clock cycle of the digital filter is determined by clock setting data for the digital filter.
When the input signal is sampled with this sampling clock and if HIGH (or LOW) is detected for
duration of four continuous clocks, the digital filter outputs HIGH (or LOW) and communicates it to
the counter circuit.
If a level changes at a frequency faster than the set-sampling-clock cycle, that level change is
invalidated and not correctly counted. Be sure to input signals which are less than the input frequency.
The cycle can be set in a range of 0.1
μ
sec through 1,056.1
μ
sec.
*The setting can be done on Web browser menu. Refer to the Reference Manual (Software) for setting
procedure.
