Contec CNT24-4D(PCI), User Manual

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I/O Port Bit Assignment
CNT24-4D(PCI)
42
Digital Filter
(Command CH0:04H, CH1:09H, CH2:0EH, CH3:13H)
04H/09H/0EH/13H
Clock data for digital filter Not in use
D7
D6 D5 D4 D3 D2 D1
D0
The digital filter allows the counter to operate normally even when
noise enters into pulses input to the counter and/or into A-, B-, and
Z-phase signals. The sampling cock cycle of the digital filter is
determined by clock setting data for the digital filter.
When the input signal is sampled with this sampling clock and if
HIGH (or LOW) is detected for a duration of four continuous
clocks, the digital filter outputs HIGH (or LOW) and communicates
it to the counter circuit.
Output the command to output port +0 and set a sampling cycle
with output port +1. The cycle can be set in a range of 0.1
µ
sec
through 1,056.1
µ
sec.
All externally input signals (except for general-purpose input
signals) are fetched through the digital filter into the internal
counter. They are fetched after a delay of four set-sampling-cycle
clocks.
When initialized, externally input signals are fetched after a delay
of 0.4
µ
sec.
* The same applies also to the LOW level.
Externally
input signal
Externally
input signal
Digital filter
Four set-sampling-cycle clocks
Input to the PC
Not valid Valid
Input to the PC
Figure 5.11. Digital filter