I/O Port Bit Assignment
CNT24-4D(PCI)
38
Asynchronous Clear
When DIR and ZSEL are set to 1, the counter is cleared to zero
when phase Z is set to high, regardless of phase A and B input
statuses. Regardless of phase Z input status, counting begins at
the next leading edge of phase A.
2
3
1
1
0
Phase A
(Phase A/UP)
Phase B
(Phase B/DOWN)
Phase Z
(Phase Z/CLR)
Count value
* When DIR is set to 0, counting down takes place at the leading edge of phase A when
phase B is set to low. When ZSEL is set to 0, counting down? is enabled when the
phase Z input is set to low.
Figure 5.8. Example counting during asynchronous clear
Summary of Contents for CNT24-4D(PCI)
Page 1: ...CNT24 4D PCI 24Bit Differencial Up Down Counter Board for PCI User s Guide ...
Page 29: ...Board Setup CNT24 4D PCI 20 ...
Page 63: ...I O Port Bit Assignment CNT24 4D PCI 54 ...
Page 66: ...Board Specifications CNT24 4D PCI 57 External Dimensions 176 4 107 0 mm ...
Page 67: ...Board Specifications CNT24 4D PCI 58 ...