Contec ADI12-16(PCI), User Manual, Page: 91 / 95

6. About Hardware
84
ADI12-16(PCI)
Timing of Sampling Control Signals
There are timing chart diagrams and a table about sampling control signals as shown Fig.6.2, 6.3, 6.4
and Table 6.5.
These timing values include a delay for the digital filter described below.
Figure 6.2. Timing Chart of External Sampling Clock
Figure 6.3. Timing Chart of External Sampling Start Control Signal
Figure 6.4. Timing Chart of External Sampling Stop Control Signal
Table 6.5. Timing Table of Operation Control Signals
Parameter Symbol Time Unit
Delay time from external sampling clock to first hold action
t
DEH
2 msec
Delay time from external sampling clock to first A/D start pulse
t
DEC
2 msec
Set up time of sampling start (Rising edge)
t
SRS
2 msec
Hold time of sampling start (Rising edge)
t
HRS
2 msec
Set up time of sampling start (Rising edge)
t
SFS
2 msec
Hold time of sampling start (Rising edge)
t
HFS
2 msec
Set up time of sampling stop (Rising edge)
t
SRP
2 msec
Hold time of sampling stop (Rising edge)
t
HRP
2 msec
Set up time of sampling stop (Rising edge)
t
SFP
2 msec
Hold time of sampling stop (Rising edge)
t
HFP
2 msec
All of the times in Table 6.2 are typical values.
t
DEC
External Smapling Clock Input
t
DEH
Conversion start
Sample / Hold
External Smapling Start Trigger Input
t
HRS
t
SRS
t
HFS
t
SFS
External Smapling Stop Trigger Input
t
HRP
t
SRP
t
HFP
t
SFP
CAUTION