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1.2 Essential Features of the Demonstration Board
Fig. 2 shows the ADC1413D125 in its environment. The output is a series CML connection capable
of delivering a throughput rate of 3.125Gsps as specified by the JESD204A standard.
The input is connected through an SMA connector and 2 transformers to adapt the impedance and
create a differential input to the ADC
The logic device Field Programmable Gate Array (FPGA) is connected to the ADC1413D125D via
2 Lanes with each lane in differential CML referenced to the positive supply. Moreover a
synchronization signal, SYNC, is routed in differential also, between the FPGA and the
ADC1413D125D.
The board contains also a flash memory as shown in Fig. 4, to store the configuration file of the
FPGA. This flash memory is loaded automatically into the logic device at start up. After the bit-stream
has downloaded into the FPGA, the diode D11 lights up indicating that everything has went well.
Fig 2.ADC1413D125 with 2 lanes in pairs of CML compliant differential
Fig 3.
FPGA Logic device connected to the ADC1413D125D via 2 Lanes and SYNC
Summary of Contents for ADC1 13D Series
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