Fig 6. shows the LEDs D9-D16 which are used to indicate the status of the FPGA.
The SYNC signal is a synchronization signal used at the beginning of the transmission. It is always
present between the FPGA and the ADC until the data is transferred from the ADC1413D125 to
the logic device . It is also used by the receiver to trigger loss of synchronization and requests re-
initialization.
The clock signal can be generated on the board as there is a Phase Locked Loop (PLL) available.
However for performance assessment we recommend to use an external clock for the FPGA and
theADC DAC. This clock should come from a unique clock generator and is known as the FRAME
clock. It is the timing reference of the circuit.
D13
FPGA clk heart beat
D14 Sync
signal
is
active
D15 K28.5
received
D16
14 bits Data are reverted
8bits by 8 bits
PUSH-A
Perform a Manual Synchronization between
FPGA and ADC
PUSH-B
Invert 14 bits parallel data Byte wise ( 8 bits by
8 bits)
Fig 6.
D13 – D16 indicates the status of the FPGA
Summary of Contents for ADC1 13D Series
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