Connect One
II-EVB-363NW User’s Manual
Appendix 6: SPI Host Interface
Introduction
The Nano WiReach contains an SPI slave port, which allows a Host processor to
interface the iChip using an SPI Master port.
The SPI data transfer shall be based on the 'Command-Response' principle. (Half
Duplex). Meaning, until the HOST gets an answer to a command, it won't send a
new one.
Several assumptions have been made:
•
Number of bits per transfer is: 8.
•
No echo from the Nano WiReach to HOST (i.e. when Nano WiReach’s
host interface is set to SPI, the command AT+iEn is meaningless.
•
When Nano WiReach’s host interface is set to SPI, Nano WiReach won't
support SerialNet mode since it is not Half Duplex compatible.
•
When Nano WiReach’s host interface is set to SPI, Nano WiReach won't
support the “+++” Escape sequence.
The SPI interface will have the following behavior:
•
Fixed peripheral select
•
The CS is directly connected to the SPI Master device
•
Mode fault detection is enabled
•
The inactive state value of the serial clock is logic level zero
•
Data is changed on the leading edge of the serial clock and captured on the
following edge of the serial clock
•
The peripheral chip select line rises as soon as the last transfer is achieved
SPI Protocol
A Nano WiReach GPIO Output signal is dedicated as the SPI Control signal
(nSPI_INT). After receiving a command from the Host, Nano WiReach will assert
this signal for the duration of its response. The Host should not attempt to send the
next command until this signal is de-asserted. The SPI control signal pin is defined
with the new +iSPIP parameter described below.
The SPI control signal is also utilized as a flow-control signal when the Host transmits
data to the Nano WiReach.
Data from Nano WiReach to Host (Slave to Master)
When Nano WiReach replies to the Host commands it sends data packets preceded by
a 2-byte header using the following structure:
1 0 0 0
4bits
MSB
8bits
LSB
Bit 15 is the Data-Ready bit 12bits Data Length
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