Congatec conga-TS170 User Manual Download Page 39

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6.2.4

USB 3.0

The conga-TS170 offers

our SuperSpeed USB 3.0 ports

on the CD connector. These ports are controlled by the

xHCI host controller provided

by the Intel

100 Series PCH . The host controller allows data transfers of up to 5 Gb/s and supports SuperSpeed, High-Speed, Full-Speed and

Low-Speed traffic.

Note

The xHCI controller supports USB debug port on all USB 3.0 capable ports.

Summary of Contents for conga-TS170

Page 1: ...COM Express conga TS170 6th Generation Intel Core i7 i5 i3 Celeron Xeon processor with either QM170 HM170 or CM236 Chipset User s Guide Revision 1 1...

Page 2: ...of pins D63 and D64 in table 31 Connector C D Pinout Corrected typographical error in section 6 1 7 PCIe Express Updated section 6 1 10 LVDS eDP Deleted all references of SDIO SD card because the chip...

Page 3: ...or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing congatec A...

Page 4: ...s unless the device is contained within its original packaging Be aware that failure to comply with these guidelines will void the congatec AG Limited Warranty Symbols The following symbols are used i...

Page 5: ...to non conformance to the agreed upon specifications will be repaired or exchanged at congatec s option and expense Customer will obtain a Return Material Authorization RMA number from congatec AG pri...

Page 6: ...documentation utilities and drivers which have been made available to assist you If you still require assistance after visiting our website then contact our technical support department by email at su...

Page 7: ...Fast Mode 29 6 1 7 PCI Express 29 6 1 8 ExpressCard 30 6 1 9 VGA 30 6 1 10 LVDS eDP 30 6 1 11 General Purpose Serial Interface 31 6 1 12 GPIOs 31 6 1 13 Power Control 31 6 1 14 Power Management 35 6...

Page 8: ...menu 90 11 4 6 Driver Health Submenu 90 11 4 7 Trusted Computing Submenu 91 11 4 8 RTC Wake Settings Submenu 91 11 4 9 ACPI Submenu 91 11 4 10 Intel ICC Submenu 92 11 4 11 AMT Configuration Submenu 93...

Page 9: ...1 1 BIOS Security Features 124 11 6 1 2 Hard Disk Security Features 127 11 7 Boot Setup 128 11 7 1 Boot Settings Configuration 128 11 8 Save Exit Menu 130 12 Additional BIOS Features 131 12 1 Support...

Page 10: ...escriptions 55 Table 18 LVDS Signal Descriptions 55 Table 19 Embedded DisplayPort Signal Descriptions 56 Table 20 SPI BIOS Flash Interface Signal Descriptions 56 Table 21 Miscellaneous Signal Descript...

Page 11: ...pinout definition and comply with COM Express 2 1 specification They are equipped with two high performance connectors that ensure stable data throughput The COM computer on module integrates all the...

Page 12: ...s 530 GT2 Intel HD Graphics 530 GT2 Intel HD Graphics 530 GT2 Intel HD Graphics 530 GT2 GFX Base Max Dynamic Freq 350 MHz 1 GHz 350 MHz 1 GHz 350 MHz 1 GHz 350 MHz 1 GHz Memory DDR4 2133 MT s dual cha...

Page 13: ...ual channel 2133 MT s dual channel LVDS Yes Yes Yes Yes DisplayPort DP Yes Yes Yes Yes HDMI Yes Yes Yes Yes VGA Yes Yes Yes Yes Processor TDP cTDP 35 W N A 25 W N A 35 W N A 25 W N A Part No 045912 EC...

Page 14: ...V5 feature the Intel Iris Pro Graphics 1x LVDS 1x Optional eDP 1 3 interface assembly option 3x DDIs Digital Display Interfaces Supports 3x DisplayPort 1 2 with support for Multi Stream Transport MST...

Page 15: ...rted Operating Systems The conga TS170 supports the following operating systems Microsoft Windows 10 Microsoft Windows 8 1 Microsoft Windows 7 Microsoft Windows Embedded Standard Linux 2 3 Mechanical...

Page 16: ...lts Input Range Volts Derated Input Volts Max Input Ripple 10Hz to 20MHz mV Max Module Input Power w derated input Watts Assumed Conversion Efficiency Max Load Power Watts VCC_12V 12 12 11 4 12 6 11 4...

Page 17: ...ue Lowest frequency mode LFM with minimum core voltage during desktop idle The CPU was stressed to its maximum frequency S0 Maximum value Highest frequency mode HFM Turbo Boost The CPU was stressed to...

Page 18: ...1 2 74 0 10 0 06 045906 ECC 4 GB A 0 BQSLR005 Windows 7 Intel Xeon E3 1505M v5 4 2 8 3 7 0 72 5 73 5 95 0 10 0 06 045907 ECC 4 GB A 0 BQSLR005 Windows 7 Intel Xeon E3 1505L v5 4 2 0 2 8 0 65 3 06 3 16...

Page 19: ...or more information refer to application note AN9_RTC_Battery_Lifetime pdf on congatec AG website at www congatec com support application notes 4 We recommend to always have a CMOS battery present whe...

Page 20: ...on Mobile Intel 100 Series PCH H MGMNT PECI PCIe Gen 3 Aux Channel DDI port D supports only HDMI if VGA is enabled PCIe Gen 3 PECI SM Bus Dual Channel DDR4 eDP PCIe Gen 3 eDP to LVDS Bridge 2x SO DIMM...

Page 21: ...ctive cooling solution CSA Passive cooling solution CSP Heatspreader The dimensions of the cooling solutions are shown below and all measurements are in millimeter The maximum torque specification for...

Page 23: ...heat generated by the module is dissipated it is not to be considered as a heatsink It has been designed as a thermal interface between the module and the application specific thermal solution The ap...

Page 24: ...ng temperature of the module is maintained at all times This may require additional cooling components for your final application s thermal solution For adequate heat dissipation use the mounting hole...

Page 25: ...her They are often referred to as the superconductors of heat as they possess an extra ordinary heat transfer capacity and rate with almost no heat loss The thermal image below provides a reference to...

Page 26: ...e Sensor The CPU temperature sensor T00 is located in the CPU U1 This sensor measures the CPU temperature and is defined in CGOS API as CGOS_TEMP_CPU The board temperature sensor T01 is located in the...

Page 27: ...de of the module This sensor measures the temperature of the DRAM module and is defined in CGOS API as CGOS_TEMP_BOTDIMM_ENV The DRAM sensor location is shown below Note The optional DRAM sensors are...

Page 28: ...ntel 100 Series PCH The SATA ports can perform DMA operation independently and are based on Serial ATA Specification revision 3 2 with up to 6 0 Gb s data transfer rates The SATA controller supports t...

Page 29: ...eries PCH There are many devices available for this Intel defined bus The LPC bus corresponds approximately to a serialized ISA bus yet with a significantly reduced number of signals Due to the softwa...

Page 30: ...DMI DVI from the BIOS menu 6 1 10 LVDS eDP The conga TS170 offers an LVDS interface with optional eDP overlay on the AB connector The LVDS eDP interface is by default configured to provide LVDS signal...

Page 31: ...eed and high speed modes The UART interfaces are routed to the AB connector and require congatec device to function Note The UART interfaces do not support legacy COM port emulation 6 1 12 GPIOs The c...

Page 33: ...ves the signal low until it is safe to let the module boot up When considering the above shown voltage divider circuitry and the transistor stage the voltage measured at the PWR_OK input pin may be on...

Page 34: ...r off The response to this signal from the system may vary as a result of modifications made in BIOS settings or by system software Standard 12V Power Supply Implementation Guidelines 12 volt input po...

Page 35: ...Sx The Deep Sx is a lower power state employed to minimize the power consumption while in S3 S4 S5 In the Deep Sx state the system entry condition determines if the system context is maintained or no...

Page 36: ...0 with support for 8 0 Gb s speed The PEG interface is by default configured as a 1x16 link You can optionally configure the PEG port to support graphics and or non graphic PCI Express devices This co...

Page 37: ...binations and resolutions Table 7 Maximum Supported Resolutions Display 1 Display 2 Display 3 External Max Resolution External Max Resolution Internal External Max Resolution Option 1 DP HDMI 4096x230...

Page 38: ...ard 6 2 3 2 DVI The conga TS170 offers three DVI ports on the CD connector These interfaces support maximum display resolutions of 1920x1200 at 60 Hz Note The conga TS170 supports up to 3 independent...

Page 39: ...n the CD connector These ports are controlled by the xHCI host controller provided by the Intel 100 Series PCH The host controller allows data transfers of up to 5 Gb s and supports SuperSpeed High Sp...

Page 40: ...d information such as serial number EAN number hardware and firmware revisions and so on It also keeps track of dynamically changing data like runtime meter and boot counter 7 3 Watchdog The conga TS1...

Page 41: ...Logo This feature allows system designers to replace the standard text output displayed during POST with their own BIOS boot logo Customized BIOS development by congatec for OEM Boot Logo is no longe...

Page 42: ...t Control Method Battery mentioned above the latest versions of the conga TS170 BIOS and board controller firmware also support LTC1760 battery manager from Linear Technology and a battery only soluti...

Page 43: ...ftware support for an external TPM by the BIOS This TPM 1 2 2 0 includes coprocessors to calculate efficient hash and RSA algorithms with key lengths up to 2 048 bits as well as a real random number g...

Page 44: ...ance features such as port independent DMA engines each device is treated as a master and hardware assisted native command queuing AHCI also provides usability enhancements such as Hot Plug and advanc...

Page 45: ...ar intervals until the upper limit is met or the maximum possible upside for the number of active cores is reached For more information about Intel Turbo Boost 2 Technology visit the Intel website Not...

Page 46: ...system use an ATX style power supply 8 2 3 Processor Performance Control Intel processors found on the conga TS170 run at different voltage frequency states performance states which is referred to as...

Page 47: ...ns do not need to be recompiled and may or may not benefit from the 64 bit extensions The application will likely need to be re certified by the vendor to run on the new 64 bit extended operating syst...

Page 48: ...should be directed to the VMM software vendor and not congatec technical support 8 2 6 Thermal Management ACPI is responsible for allowing the operating system to play an important part in the system...

Page 49: ...t to S3 USB hardware must be powered by standby power source Set USB Device Wakeup from S3 S4 to Enabled in the ACPI setup menu if setup node is available in BIOS setup program In Device Manager look...

Page 50: ...ors only pull ups or pull downs implemented by congatec are listed For information about the internal pull ups or pull downs implemented by the chip vendors refer to the respective chip s datasheet Ta...

Page 51: ...N2 is not connected Note Some signals have special functionality during the reset process They may bootstrap some basic important functions of the module For more information refer to section 8 5 of t...

Page 52: ...cation Revision 3 0 SATA1_RX SATA1_RX B19 B20 Serial ATA channel 1 Receive Input differential pair I SATA Supports Serial ATA specification Revision 3 0 SATA1_TX SATA1_TX B16 B17 Serial ATA channel 1...

Page 53: ...IE Supports PCI Express Base Specification Revision 3 0 PCIE_TX3 PCIE_TX3 A58 A59 PCI Express channel 3 Transmit Output differential pair O PCIE Supports PCI Express Base Specification Revision 3 0 PC...

Page 54: ...a or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB5 B39 USB Port 5 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB6 A37 USB Port 6 data or D I O USB 2 0 compliant Bac...

Page 55: ...6 DDC data line I O OD 5V PU 1k2 3 3V Optional Table 18 LVDS Signal Descriptions Signal Pin Description I O PU PD Comment LVDS_A0 LVDS_A0 LVDS_A1 LVDS_A1 LVDS_A2 LVDS_A2 LVDS_A3 LVDS_A3 A71 A72 A73 A7...

Page 56: ...Flash Interface Signal Descriptions Signal Pin Description I O PU PD Comment SPI_CS B97 Chip select for Carrier Board SPI BIOS Flash O 3 3VSB Carrier shall pull to SPI_POWER when external SPI is prov...

Page 57: ...wn This signal is used to indicate Physical Presence to the TPM I 3 3V Trusted Platform Module chip is optional Note Some signals have special functionality during the reset process They may bootstrap...

Page 58: ...y O 3 3VSB SUS_S4 A18 Indicates system is in Suspend to Disk state Active low output O 3 3VSB Not supported SUS_S5 A24 Indicates system is in Soft Off state O 3 3VSB WAKE0 B66 PCI Express wake up sign...

Page 59: ...CC_12V A104 A109 B104 B109 Primary power input 12V nominal All available VCC_12V pins on the connector s shall be used P VCC_5V_SBY B84 B87 Standby power input 5 0V nominal If VCC5_SBY is used all ava...

Page 60: ...0 A17 SATA0_TX B17 SATA1_TX A72 eDP_TX2 LVDS_A0 B72 LVDS_B0 A18 SUS_S4 B18 SUS_STAT A73 eDP_TX1 LVDS_A1 B73 LVDS_B1 A19 SATA0_RX B19 SATA1_RX A74 eDP_TX1 LVDS_A1 B74 LVDS_B1 A20 SATA0_RX B20 SATA1_RX...

Page 61: ...VD A45 USB0 B45 USB1 A100 GND FIXED B100 GND FIXED A46 USB0 B46 USB1 A101 SER1_TX B101 FAN_PWMOUT A47 VCC_RTC B47 EXCD1_PERST A102 SER1_RX B102 FAN_TACHIN A48 EXCD0_PERST B48 EXCD1_CPPE A103 LID B103...

Page 62: ...e signal differential pairs for the Superspeed USB data path I USB_SSRX0 C3 I USB_SSTX0 D4 Additional transmit signal differential pairs for the Superspeed USB data path O USB_SSTX0 D3 O USB_SSRX1 C7...

Page 63: ...G_RX7 PEG_RX7 PEG_RX8 PEG_RX8 PEG_RX9 PEG_RX9 PEG_RX10 PEG_RX10 PEG_RX11 PEG_RX11 PEG_RX12 PEG_RX12 PEG_RX13 PEG_RX13 PEG_RX14 PEG_RX14 PEG_RX15 PEG_RX15 C52 C53 C55 C56 C58 C59 C61 C62 C65 C66 C68 C6...

Page 64: ...5 D78 D79 D81 D82 D85 D86 D88 D89 D91 D92 D94 D95 D98 D99 D101 D102 PCI Express Graphics Transmit Output differential pairs Note Can also be used as PCI Express Transmit Output differential pairs 16 t...

Page 65: ...OD 3 3V PD100k DDI1_CTRLDATA_AUX D16 Multiplexed with DP1_AUX and HDMI1_CTRLDATA DP AUX function if DDI1_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high I O PCIE I...

Page 66: ...LANE3 and TMDS3_CLK O PCIE DDI3_HPD C44 Multiplexed with DP3_HPD and HDMI3_HPD I 3 3V PD 1M DDI3_CTRLCLK_AUX C36 Multiplexed with DP3_AUX and HDMI3_CTRLCLK DP AUX function if DDI3_DDC_AUX_SEL is no co...

Page 67: ...I TMDS differential pair Multiplexed with DDI2_PAIR2 and DDI2_PAIR2 O PCIE TMDS2_DATA1 TMDS2_DATA1 D42 D43 HDMI DVI TMDS differential pair Multiplexed with DDI2_PAIR1 and DDI2_PAIR1 O PCIE TMDS2_DATA2...

Page 68: ...chronous streams and secondary data Multiplexed with DDI1_PAIR0 and DDI1_PAIR0 O PCIE DP1_HPD C24 Detection of Hot Plug Unplug and notification of the link layer Multiplexed with DDI1_HPD I 3 3V PD 1M...

Page 69: ...3_LANE1 C42 C43 Uni directional main link for the transport of isochronous streams and secondary data Multiplexed with DDI3_PAIR1 and DDI3_PAIR1 O PCIE DP3_LANE0 DP3_LANE0 C39 C40 Uni directional main...

Page 70: ...oard logic may also implement a fault indicator such as an LED TYPE10 A97 Dual use pin Indicates to the carrier board that a Type 10 module is installed Indicates to the carrier that a Rev 1 0 2 0 mod...

Page 71: ...DDI1_PAIR6 D16 DDI1_CTRLDATA_AUX C71 PEG_RX6 D71 PEG_TX6 C17 RSVD D17 RSVD C72 PEG_RX6 D72 PEG_TX6 C18 RSVD D18 RSVD C73 GND D73 GND C19 PCIE_RX6 D19 PCIE_TX6 C74 PEG_RX7 D74 PEG_TX7 C20 PCIE_RX6 D20...

Page 72: ...C99 PEG_RX14 D99 PEG_TX14 C45 RSVD D45 RSVD C100 GND FIXED D100 GND FIXED C46 DDI3_PAIR2 D46 DDI2_PAIR2 C101 PEG_RX15 D101 PEG_TX15 C47 DDI3_PAIR2 D47 DDI2_PAIR2 C102 PEG_RX15 D102 PEG_TX15 C48 RSVD D...

Page 73: ...is a boot strap signal see note below DDI2_CTRLDATA_AUX DP2_AUX HDM2_CTRLDATA C33 Multiplexed with DP2_AUX and HDMI2_CTRLDATA DP AUX function if DDI2_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLDATA i...

Page 74: ...l I O cycles that are not positively decoded are forwarded to the PCI Bus not the LPC Bus Only specified I O ranges are forwarded to the LPC Bus In the congatec Embedded BIOS the following I O address...

Page 75: ...Note1 16h 02h ME IDE Redirection IDE R Interface 00h Note1 16h 03h ME Keyboard and Text KT Redirection 00h Note1 16h 04h Intel ME Interface 3 00h 17h 00h SATA Controller 00h 1Ch 00h Not connected PCI...

Page 76: ...sible only if a device is attached to the PCI Express Slot on the carrier board 3 The table represents a case when a single function PCI PCIe device is connected to all possible slots on the carrier b...

Page 77: ...perator to select either the boot device that should be used or an option to enter the BIOS setup program 11 2 Setup Menu and Navigation The congatec BIOS setup screen is composed of the menu bar and...

Page 78: ...Main screen reports BIOS processor memory and board information and is used to configure the system date and time Feature Options Description BIOS Information Main BIOS Version No option Displays the...

Page 79: ...Speed No option Displays the processor speed Processor Signature No option Displays the processor signature Stepping No option Displays the processor stepping Processor Cores No option Displays the nu...

Page 80: ...og Module Serial Ports Hardware Health Monitoring Intel Ethernet Connection H I219 LM Driver Health Trusted Computing RTC Wake Settings ACPI Intel ICC AMT Configuration PCH FW Configuration SMART Sett...

Page 81: ...CIe Uses a PCI PCIe graphics card attached to a PCI PCIe port Primary PEG Auto PEG1 PEG2 Select which graphics device should be Primary PEG Auto selects PEG 0 as primary PEG Primary PCIE Auto PCIE1 PC...

Page 82: ...XGA 1024x768 2x18 007h XGA 1024x768 1x24 008h XGA 1024x768 2x24 012h WXGA 1280x800 1x18 01Eh WXGA 1280x768 1x24 01Ch SXGA 1280x1024 2x24 00Ah SXGA 1280x1024 2x24 018h UXGA 1600x1200 2x24 00Ch HD 1920...

Page 83: ...he SoC according this setup node This feature may help to avoid panel flickering LVDS SSC Disabled 0 5 1 0 1 5 2 0 2 5 Select LVDS spread spectrum clock modulation depth Note Performs center spreading...

Page 84: ...1024MB 2048MB 4096MB Select the aperture size Note To use this feature disable CSM support Above 4GB MMIO BIOS assignment is automatically enabled when selecting 2048MB aperture IGD Pre Allocated Gra...

Page 85: ...ght Setting No Yes Set Yes to invert backlight control values Note This feature may be required for the actual I2C type backlight hardware controller 11 4 1 1 Display Interface Signal Integrity Settin...

Page 86: ...ng Pre Emphasis levels DDI 3 IBoost Disabled Enabled Enables the IBoost for selected port on all the VSwing Pre Emphasis levels 11 4 2 Watchdog Submenu Feature Options Description POST Watchdog Disabl...

Page 87: ...that will be generated when timeout 3 is reached Timeout 1 1sec 2sec 5sec 10sec 30sec 1min 2min 5min 10min 30min Select the timeout value for the first stage watchdog event Timeout 2 see above Select...

Page 88: ...8h 238h 2E8h 338h 3E8h Set serial port base address Interrupt None IRQ3 IRQ4 IRQ5 IRQ6 IRQ14 IRQ15 Set serial port interrupt PNP ID None PNP0501 CGT0501 Set serial port ACPI ID Baudrate 2400 4800 9600...

Page 89: ...module board temperature in C DC Input Voltage No option Displays the actual voltage of the standard DC power supply 5V Standby No option Displays the actual voltage of the 5V standby power rail DC In...

Page 90: ...ion Displays the PCI Device ID of the Ethernet controller PCI Address No option Displays the PCI Bus Device Function number of the Ethernet controller Link Status No option Displays the Link Status MA...

Page 91: ...Enter 3 for 3am and 15 for 3pm Wake up minute 0 Specify wake up minute Wake up second 0 Specify wake up second 11 4 9 ACPI Submenu Feature Options Description Enable ACPI Auto Configuration Disabled...

Page 92: ...he critical trip point manually Critical Trip Point Value 71 C 79 C 87 C 95 C 100 C 103 C 111 C 119 C 127 C Select the temperature threshold at which the ACPI aware operating system performs a critica...

Page 93: ...firmation Disabled Enabled Hide Un Configure ME without password confirmation prompt MEBx Debug Message Output Disabled Enabled Enable or disable MEBx debug message output Un Configure ME Disabled Ena...

Page 94: ...h Selection GPDMA Work Around MSFT QFE Solution Selects the desired fTPM solution to be used TPM Device Selection dTPM 1 2 PTT Select TPM device PTT Enables PTT and disables dTPM in SkuMgr dTPM 1 2 En...

Page 95: ...Device Settings IO 378h IRQ 5 Displays the currently used settings Device Mode STD Printer Mode SPP Mode EPP 1 9 and SPP Mode EPP 1 7 and SPP Mode ECP Mode ECP and EPP 1 9 Mode ECP and EPP 1 7 Mode Se...

Page 96: ...e Baudrate 9600 19200 38400 57600 115200 Select baud rate Data Bits 7 8 Set the number of data bits Parity None Even Odd Mark Space Select the parity Stop Bits 1 2 Set the number of stop bits Flow Con...

Page 97: ...CPU Speed No option Displays the current CPU speed Processor Cores No option Displays the number of the processor cores Intel HT Technology No option Displays whether Intel HT technology is supported...

Page 98: ...d Enabled Enable this feature to expose the CPPC v2 interface allowing hardware controlled P states Intel SpeedStep tm Disabled Enabled Enable this feature if you require support for more than two fre...

Page 99: ...nter C State C State Auto Demotion Disabled C1 C3 C1 and C3 Configure C State Auto Demotion C State Un demotion Disabled C1 C3 C1 and C3 Configure C State Un demotion Package C State Demotion Disabled...

Page 100: ...es EC reported temperature values Enabled ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values Out of Spec ACPI Thermal Management uses EC reported temperature values and DT...

Page 101: ...A Mode Selection AHCI RAID Select SATA controller mode Note RAID option is not supported on all chipsets CR 1 RST Pcie Storage Remapping Enabled Disabled Enable or disable RST PCIe storage remapping C...

Page 102: ...e is connected to it Software Preserve No option Indicates whether the detected drive supports software settings preservation SATA Port Disabled Enabled Enable or disable the relevant SATA port Hot Pl...

Page 103: ...sks and RAID volumes are normal HDD Unlock Disabled Enabled If this feature is enabled the HDD password unlock option is available in the operating system LED Locate Disabled Enabled Enable or disable...

Page 104: ...Disk drive name Acoustic Mode Bypass Quiet Max Performance Same as at SATA Port 0 SATA Port 2 Disk drive name Acoustic Mode Bypass Quiet Max Performance Same as at SATA Port 0 SATA Port 3 Disk drive n...

Page 105: ...t Reset VC TC Mapping Disabled Enabled If the system has Virtual Channels software can reset traffic class mapping to its default state through virtual channels Note Enabling this feature will not mo...

Page 106: ...r disable PCI Express clock gating for each root port DMI Link ASPM Processor Side Disabled Enabled Enable or disable Active State Power Management of the DMI link on the processor side Port8xh Decode...

Page 107: ...bmenu PCI Express port 2 settings PCI Express Port 3 Submenu PCI Express port 3 settings PCI Express Port 4 Submenu PCI Express port 4 settings PCI Express Port 5 Submenu PCI Express port 5 settings P...

Page 108: ...previous training attempt was unsuccessful Link Training Timeout us 1000 Defines the number of microseconds software will wait before polling link training bit in the link status register Value range...

Page 109: ...pported by hardware and set to Enabled this function will block forwarding of TLPs containing End End TLP Prefixes PCI Express GEN2 Link Register Settings Target Link speed Auto Force to 2 5 GT s Forc...

Page 110: ...or disable PCI Express Device Fatal Error Reporting NFER Disabled Enabled Enable or disable PCI Express Device Non Fatal Error Reporting CER Disabled Enabled Enable or disable PCI Express Device Corr...

Page 111: ...PCH PCIe Non Snoop Latency Override Disabled Manual Auto Non Snoop Latency Override for PCH PCIe 11 4 21 5 PCI Express Graphics PEG Port Submenu Feature Options Description PEG Port Configuration 1x16...

Page 112: ...emphasis Control 6 dB 3 5 dB Set the de emphasis control on PEG OBFF Disabled Enabled Enable or disable CPU PEG0 0 1 0 OBFF LTR Disabled Enabled Enable or disable CPU PEG0 0 1 0 latency reporting PEG...

Page 113: ...0 1 14 15 can be set individually Gen3 Adaptive Software Equalization Always Attempt SW EQ Enabled Disabled Enable to always attempt SW EQ even it has been done once Number of Presets to test Auto 0 9...

Page 114: ...ways Gate A20 cannot be disabled Note This feature is useful if runtime code above 1MB is executed Option ROM Messages Force BIOS Keep Current Set display mode for option ROMs INT19 Trap Response Imme...

Page 115: ...tion on all USB ports USB Precondition Disabled Enabled Enable or disable USB Precondition precondition makes enumeration faster XHCI Disable Compliance Mode FALSE TRUE Options to disable Compliance M...

Page 116: ...be redirected Primary Port Addr Lowbyte Dec 0 255 128 Set the address for the primary debug port The usual address value is 0x80 i e 128 dec lowbyte and 0 highbyte However any multiple of 8 is valid...

Page 117: ...d 38400 Baud Choose the baudrate for the BC Diagnostic Console interface 11 4 28 PC Speaker Submenu Feature Options Description Debug Beeps Disabled Enabled Enable or disable general debug status beep...

Page 118: ...ble VT d support Note This feature is only displayed if the processor supports VT d capability Thermal Device B0 D4 F0 Enabled Disabled Enable or disable thermal device GMM Device B0 D8 F0 Enabled Dis...

Page 119: ...eset Value for each Lane Submenu In this submenu the root port preset value for lanes 0 3 can be set individually Gen3 Endpoint Preset Value for each Lane Submenu In this submenu the endpoint preset v...

Page 120: ...r disable MRC ULT Safe Config for PO Maximum Memory Frequency Auto 1067 1333 1600 1867 2133 2400 2667 2933 3200 Set the maximum memory frequency selections in MHz Note This feature is hidden if DIMM p...

Page 121: ...3 Select the bit for channel interleaved mode Note BIT07 interleaves the channels at a 2 cacheline granularity BIT08 at 4 and BIT09 at 8 VC1 Read Metering Enabled Disabled Enable or disable VC1 Read M...

Page 122: ...reset either the host partition only or both the host and Intel ME partition HD Audio Configuration Submenu Opens submenu to configure HD audio TraceHub Configuration Menu Submenu Opens submenu to con...

Page 123: ...word dword decoding of port 80h behind LPC Compatible Revision ID Disabled Enabled Enable or disable the PCH compatible revision ID feature PCH Cross Throttling Enabled Disabled Enable or disable the...

Page 124: ...ty feature set Select the device to open its security configuration submenu Secure Boot Menu Submenu 11 6 1 1 BIOS Security Features BIOS Password BIOS Write Protection ABIOSpasswordprotectstheBIOSset...

Page 125: ...e Boot Secure Boot is a security standard defined in UEFI specification 2 3 1 that helps prevent malicious software applications and unauthorized operating systems from loading during system start up...

Page 127: ...d The max length of the passwords is 32 bytes During POST each hard drive is checked for security mode feature support In case the drive supports the feature and it is locked the BIOS prompts the user...

Page 128: ...on is pressed Turn On Restores power to the computer Last State Restores the power state before power loss occurred Note This feature only works with an ATX type power supply AT Shutdown Mode System R...

Page 129: ...to UEFI Driver Auto Installs legacy video option ROM for legacy operating system boot Note The boot logo will not be displayed during POST UEFI Driver Installs UEFI GOP driver USB Support Disabled Ful...

Page 130: ...cription Save Changes and Exit Exit setup menu after saving the changes The system is only reset if settings have been changed Discard Changes and Exit Exit setup menu without saving any changes Save...

Page 131: ...evision number The BQSL binary size is 16 MB and the BHSL binary size is 8 MB 12 1 Supported Flash Devices The conga TS170 supports the following flash devices Winbond W25Q128FVSIG 16 MB Winbond W25Q6...

Page 132: ...on Revision 1 0 LPC http developer intel com design chipsets industry lpc htm Universal Serial Bus USB Specification Revision 2 0 http www usb org home PCI Specification Revision 2 3 http www pcisig c...

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