2.0 Functional Description
Fusion 878A
2.11 Video and Control Data FIFO
PCI Video Decoder
2-32
Conexant
100600B
2.11 Video and Control Data FIFO
The FIFO block accepts data from the video data format conversion process,
buffers the data in FIFO memory, then outputs DWORDs to the DMA Controller
to be burst onto the PCI bus.
2.11.1 Logical Organization
The 630-byte data FIFO is logically organized into three segments:
1.
FIFO1 = 70 words deep by 36 bits wide
2.
FIFO2 = 35 × 36 bits
3.
FIFO3 = 35 × 36 bits
Each of the 140 FIFO data words provide for one DWORD of pixel data and
four bits of video control code status. This is illustrated in
FIFOs are large enough to support efficient size burst transfers (16 to 32 data
phases) in planar as well as packed mode.
Figure 2-20. Data FIFO Block Diagram
FIFO1
70 x 36
FIFO2
35 x 36
FIFO3
35 x 36
Y
Cr
Cb
FIFO Write Signals
(From VDFC)
FIFO Enable Signal
(From Control
FIFO Write Clock
(Synchronous to
Video Decoder
FIFO1
Output
FIFO2
Output
FIFO3
Output
FIFO Read Signals
(From DMA Controller)
FIFO Read Clock
(Synchronous to
PCI Clock)
From FIFO Input Data Formatter
FI[35:32]
Control Status Code
FI[31:0]
Pixel Data
Pixel Clock)
3
3
Register)
879A_025
