Registers
A-25
Figure A-35 RCIM II Interrupt Enable/Request/Pending/Clear/Arm/Level/Polarity Registers
(IER, IRR, IPR, ICR, IAR, ISLR, ISPR)
The enable registers (IER) enable the selected interrupts.
The request registers (IRR) are software driven requests of the selected interrupts.
The pending registers (IPR) are pending requests.
The clear registers (ICR) clear the selected interrupts.
The arm registers (IAR) arm the selected interrupts for edge triggering.
The level registers (ISLR) set level (1) or edge (0) for the selected interrupts.
The polarity registers (ISPR) set polarity high (1) or low (0) for the selected interrupts.
Offsets: IER1: 0010, IER2: 0014, IRR1/IPR1: 0020, IRR2/IPR2: 0024, ICR1: 0030, ICR2: 0034,
IAR1: 0040, IAR2: 0044, ISLR1: 0050, ISLR2: 0054, ISPR1: 0060, ISPR2: 0064
Register #1
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CI
AUX
Reserved
EI
RTC
7
6
5
4
3
2
1
0
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CI
=
Cable Interrupt
AUX =
Auxiliary Interrupt (GPS)
EI
=
External Interrupt
RTC =
RTC Interrupt
Register #2
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
CI
Reserved
EI
Reserved
11 10 9
8
11 10 9
8
AUX2 = GPS_BX_FULL
AUX1 = GPS_TX_EMPTY
AUX3 =
Reserved
AUX0 = GPS_PPS
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